One of 3-D devices to achieve high density arrays was adopted in this study, where source and drain junctions are formed along the silicon fin. The screening by adjacent high fins for large sensing margin makes it hard to ion-implant with high angle so that vertical ion implantation is inevitable. In this study, the dependency of current characteristics on doping profiles is investigated by 3-D numerical analysis. The position of concentration peak and the doping gradient are varied to look into the effects on driving currents. Through these analyses, the optimum condition of ion implantation for 3-D devices is estimated.

We determine the annealing dynamics of AsGa antisite defects in As ion-implanted GaAs. An Arrhenius plot of the carrier decay rate or the defect density vs. the annealing temperature in the high temperature regime gives an energy EPA, which is different from true activation energy. The annealing time dependence of EPA obtained by the two diffusion models (self diffusion of AsGa antisite defects and VGa vacancy assisted diffusion of AsGa antisite defects) are compared with EPA's obtained from already published works. The results prove that the diffusion of AsGa antisite defects is assisted by the VGa vacancy defects that exist in a high density.

The high accuracy which is necessary for modern process simulation often requires the use of Monte-Carlo ion implantation simulation methods with the disadvantage of very long simulation times especially for three-dimensional applications. In this work a new method for an accurate and CPU time efficient three-dimensional simulation of ion implantation is suggested. The approach is based on a combination of the algorithmic capabilities of a fast analytical and the Monte-Carlo simulation method.

This paper outlines the modeling requirements of integrated circuit (IC) fabrication processes that have lead to and sustained the development of computer-aided design of technology (i. e. TCAD). Over a period spanning more than two decades the importance of TCAD modeling and the complexity of required models has grown steadily. The paper also illustrates typical applications where TCAD has been powerful and strategic to IC scaling of processes. Finally, the future issues of atomic-scale modeling and the need for an hierarchical approach to capture and use such detailed information at higher levels of simulation are discussed.

A novel method has been developed to improve the dry etching selectivity of aluminum alloy with respect to photoresist by implanting ions into the patterned photoresist. The selectivity becomes 7.5, which is 5 times higher than that of the unimplanted case. Accordingly, this technology is very promising for fabricating multi-level interconnections in sub-half micron LSIs.

A novel technique for evaluation of charge build-up in semiconductor wafer processing such as ion implantation, plasma etching and plasma enhanced chemical vapor deposition by using the breakdown of MOS capacitors with charge collecting electrodes (antenna) is proposed. The charge build-up during high beam current ion implantation is successfully evaluated by using this technique. The breakdown sensitivity of a MOS capacitor is improved by using a small area MOS capacitor with a large area antenna electrode. To estimate charge build-up on wafers quantitatively, the best combination of gate oxide thickness, substrate type, MOS capacitor area and antenna ratio should be carefully chosen for individual charge build-up situation. The optimum structured antenna MOS capacitors which relationship between QBD and stressing current density was well characterized give us very simple and quantitative charge build-up evaluation. This technique is very simple and useful to estimate charge build-up as compared with conventional technique by suing EEPROM devices or large area MOS capacitors.

The Double-Sided Rugged poly Si (DSR) technology has been developed for high density DRAMs. The DSR technology was achieved using transformation of rugged poly Si caused by ion implantation. The DSR can increase the surface area of the storage electrode, because it has rugged surfaces on both upper and lower sides. The 2-FINs STC (STacked Capacitor cell) with DSR was fabricated in the cell size of 0.72 µm2, and it is confirmed that the DSR can increase the surface area 1.8 times larger than that of smooth poly Si. It is expected that 25 fF/bit is obtained with a 300 nm-thick storage electrode. These effects show that sufficient capacitance for 256 Mb DRAMs is obtained with a low storage electrode. It is confirmed that there is no degradation in C-V and I-V characteristics. Moreover, the DSR needs neither complicated process steps nor special technologies. Therefore, the DSR technology is one of the most suitable methods for 256 Mb DRAMs and beyond.

We developed piezoresistors with an intrinsic compensation of the offset temperature characteristics. High energy ion implantation was applied to fabricate this type of piezoresistor. The dopant profile of the buried piezoresistor resembles to that of the junction gate field effect transistor (JFET). The buried layer corresponds to a channel of JFET, and the substrate bias corresponds to the gate voltage. Owing to the independent temperature varying parameters, i.e., width of the depletion layer and carrier mobility in the channel, the drain current of the JFET has a temperature independent point at an appropriate gate source voltage. The effect was used in the new type of buried piezoresistor which has a driving point of zero temperature coefficient of resistance at an appropriate gate source voltage.

This paper describes small AlGaAs/GaAs HBT's for low-power and high-speed integrated circuits. The device fabrication is based on a new bridged base electrode technology that permits emitter width to be defined down to 1 µm. The new technology features oxygen-ion implantation for emitter-base junction isolation and zinc diffusion for extrinsic base formation. The oxygen-ion implanted emitter-base junction edge has been shown to provide a periphery recombination current much lower than that for the previous proton implanted edgs, the result being a much higher current gain particularly in small devices. The zinc diffusion offers high device yield and good uniformity in device characteristics even for a very thin (0.04 µm) base structure. An HBT with emitter dimensions of 12.4 µm2 yields an fT of 103 GHz and an fmax of 62 GHz, demonstrating that the new technology has a significant advantage in reducing the parasitic elements of small devices. Fabricated one-by-eight static frequency dividers and one-by-four/one-by-five two-modulus prescalers operate at frequencies over 10 GHz. The emitters of HBT's used in the divider are 12.4 µm2 in size, which is the smallest ever reported for AlGaAs/GaAs HBT IC's. These results indicate that the bridged base electrode technology is promising for developing a variety of high-speed HBT IC's.

We report the development of high-performance small-scale AlGaAs/GaAs collector-up heterojunction bipolar transistors (C-up HBT) with a carbon (C)-doped base layer. Oxygen-ion (O+) implantation is used to define their intrinsic emitter/base junctions and zinc (Zn)-diffusion is used to lower the resistivity of their O+-implanted extrinsic base layers. The highly resistive O+-implanted AlGaAs layer in the extrinsic emitter region sufficiently suppresses electron injection even under high-forward-bias conditions, allowing high collector current densities. The use of a C-doped base is especially effective for small-scale C-up HBT's because it suppresses the undesirable turn-on voltage shift caused by base dopant diffusion in the intrinsic area around the collector-mesa perimeter that occurs during the high-temperature Zn-diffusion process after implantation. Even in a small-scale trasistor with a 2 µm2 µm collector, a current gain of 15 is obtained. A microwave transistor with a 2 µm10 µm collector has a cutoff frequency fT of 68 GHz and a maximum oscillation frequency fmax of 102 GHz. A small-scale C-up HBT with a 2 µm2 µm collector shows a higher fmax of 110 GHz due to reduced base/collector capacitance CBC and its fmax remains above 100 GHz, even at a low collector current of 1 mA. The CBC of this device is estimated to be as low as 2.2 fF. Current gain dependence on collector size is also investigated for C-up HBT's and it is found that the base recombination current around the collector-mesa perimeter reduces the current gain.

The dielectric breakdown characteristics of a thin gate oxide during high-current ion implantation with an electron shower have been investigated by controlling the energy distribution of the electrons. Degradation of the oxide has also been discussed with regard to the total charge injected into the oxide during ion implantation in comparison with that of the TDDB (time dependent dielectric breakdown). Experimental results show that the high-energy and high-density electrons which concentrated in the circumference of the ion beam due to the space charge effect cause the degradation of the thin oxide. It was confirmed that eliminating the high-energy electrons by applying magnetic and electric fields lowers the electron energy at the wafer surface, thereby effectively suppressing the negative charge-up.

A fully three-dimensional simulation tool for modeling the ion implantation in arbitrarily complex three-dimensional structures is described. The calculation is based on the Monte Carlo (MC) method. For MC simulations of realistic three-dimensional structures the key problem is the CPU-time consumption which is primarily caused by two facts. (1) A large number of ion trajectories (about 107) has to be simulated to get results with reasonable low statistical noise. (2) The point location problem is very complex in the three-dimensional space. Solutions for these problems are given in this paper. To reduce the CPU-time for calculating the numerous ion trajectories a superposition method is applied. For the point location (geometry checks) different possibilities are presented. Advantages and disadvantages of the conventional intersection method and a newly introduced octree method are discussed. The octree method was found to be suited best for three-dimensional simulation. Using the octree the CPU-time required for the simulation of one ion trajectory could be reduced so that it only needs approximately the same time as the intersection method in the two-dimensional case. Additionally, the data structure of the octree simplifies the coupling of this simulation tool with topography simulators based on a cellular method. Simulation results for a three-dimensional trench structure are presented.

Diffusion of phosphorus impurities from a polycrystalline silicon films into a silicon substrate was investigated as a function of the mean concentration of phosphorus in a polycrystalline silicon film at the first diffusion stage. We presented that good control of the redistribution of implanted phosphorus impurities was possible by optimizing the normalized dose, which is the value: [the total dose of phosphorus impurities]/[the polycrystalline silicon film thickness], in the case of samples both with and without an arsenic doped layers. In the range where the normalized dose was less than 1.52.51020 cm-3, deeper junctions were formed in samples with an arsenic doped layer. In the range where the normalized dose was more than 1.52.51020 cm-3, however, deeper junctions were formed in samples without any arsenic doped layer rather than in samples with an arsenic doped layer. These results mean that formation of the junction in the device structure where a high concentration phosphorus doped polysilicon layer is stacked on to the high concentration arsenic layer embeded at the surface of the substrate can be restricted by optimizing the normalized dose. Moreover, a trade-off relationship between suppressing phosphorus diffusion and maintaining low contact resistance against normalized doses was also observed.

A new channel stop design for submicton local oxidation of silicon (LOCOS) isolation was presented. The n-channel stop was designed with boron implanation after forming LOCOS, while the p-channel stop was constructed with high energy phosphorus or arsenic implantation before or after forming LOCOS. These optimized channel stop designs can extend an isolation spacing to the submicron region without a decrease in junction breakdown voltage and an increase in junction leakage current. Narrow channel effects were found to be effectively suppressed by optimum channel stop design issues.