One of 3-D devices to achieve high density arrays was adopted in this study, where source and drain junctions are formed along the silicon fin. The screening by adjacent high fins for large sensing margin makes it hard to ion-implant with high angle so that vertical ion implantation is inevitable. In this study, the dependency of current characteristics on doping profiles is investigated by 3-D numerical analysis. The position of concentration peak and the doping gradient are varied to look into the effects on driving currents. Through these analyses, the optimum condition of ion implantation for 3-D devices is estimated.

A novel asymmetric MOSFET with no LDD on the source side is simulated on bulk-Si using a device simulator (SILVACO). In order to overcome the problems of the conventional asymmetric process, a novel asymmetric MOSFET using mesa structure and sidewall spacer gate is proposed which provides self-alignment process, aggressive scaling, and uniformity. First of all, we have simulated to compare the characteristics between asymmetric and symmetric MOSFETs. Basically, both asymmetric and symmetric MOSFETs have an n-type channel (25-nm) and the same physical parameters. When we compare this with the 25-nm symmetric MOSFET, the proposed asymmetric MOSFET shows better device performances.