Differential Evolution (DE) algorithm is simple and effective. Since DE has been proposed, it has been widely used to solve various complex optimization problems. To further exploit the advantages of DE, we propose a new variant of DE, termed as ranking-based differential evolution (RDE), by performing ranking on the population. Progressively better individuals in the population are used for mutation operation, thus improving the algorithm's exploitation and exploration capability. Experimental results on a number of benchmark optimization functions show that RDE significantly outperforms the original DE and performs competitively in comparison with other two state-of-the-art DE variants.

A primary-side regulation AC--DC constant voltage control chip is designed, which employs a novel cable compensation technique to improve the precision of the output voltage and pursue a wider load range for regulation. In the proposed controller, constant voltage (CV) is achieved by OSC charging current and current-limiting point adjustment. Meantime, according to different cable lengths, the sampled voltage is regulated by injecting current to pull-down resistance of the system to obtain an accurate output voltage. The proposed chip is implemented in TSMC 0.35,$mu $m 5,V/40,V BCD process, and a 12,V/1,A circuit prototype has been built to verify the proposed control method. Experimental results show that the maximum cable compensation current reaches 43,$mu $A, and the precision of the output voltage is within $pm$ 3% in a wide range of output current from 0 to 1,A.

Based on the semiclassical theory, we deduce the expressions of stimulated absorption, stimulated amplification and threshold by using density matrix equation in the Er3+-doped fibers. Meaningful results have been given and some phenomena occuring in experiments are explained theoretically.

A hardware description languages (HDLs) based modeling technique for asynchronous circuits is presented in this paper. A HDLs handshake package has been developed for expressing handshake-style digital systems in both VHDL and Verilog. Burst-mode and extended burst-mode (BM/XBM) circuits were used to demonstrate the usefulness of this work. This research successfully prototyped comparators, adders, RSA encoder/decoder, and several self-timed circuits for the full-custom IC and FPGAs designs. Furthermore, the HDLs handshake package implemented by this research can be utilized to develop behavioral test benches for studying and analyzing asynchronous designs. Extracting detailed timing information from asynchronous finite state machines (AFSMs), detecting delay faults for synthesized self-timed functional modules, and locating fundamental mode violation within realized AFSMs are proven applications. The anticipated HDL modeling technique and the transformation procedure are detailed in the rest of this paper.

This letter evaluates the relative contributions of temporal fine structure cues in various frequency bands to Mandarin tone perception using novel "auditory chimaeras". Our results confirm the importance of temporal fine structure cues to lexical tone perception and the dominant region of lexical tone perception is found, namely the second to fifth harmonics can contribute no less than the fundamental frequency itself.

In this paper, we report the recent progress in visible light positioning and communication systems using light-emitting diodes (LEDs). Due to the wide deployment of LEDs for indoor illumination, visible light positioning (VLP) and visible light communication (VLC) using existing LEDs fixtures have attracted great attention in recent years. Here, we review our recent works on visible light positioning and communication, including image sensor-based VLP, photodetector-based VLP, integrated VLC and VLP (VLCP) systems, and heterogeneous radio frequency (RF) and VLC (RF/VLC) systems.

Our paper proposes a low power delay element with many other valuable characteristics for asynchronous circuits in the bundled-data implementation. Delay elements are frequently utilized to interact with asynchronous environment for revealing the current status of the bundled-data asynchronous circuits. Thus, a notable portion of the total energy is consumed by the delay elements for this kind of designs. Moreover, constructing a specific delay on a chip is a difficult task for recent CMOS technology. An extreme low power asymmetrical delay element with post-chip adjustment feature was developed mainly for solving these issues. Our initial intention was to develop a programmable delay element for asynchronous data path components. The proposed delay element is also suitable for many other applications requiring low power constraint. In addition to the programmability, the delay element also demonstrated efficiently characteristics such as good tolerance to process and temperature variations on the delay. Our delay element is equivalent to approximately the average power of a 4-stage inverter chain. A large delay can be obtained by cascaded scheme with nearly zero handshaking overhead. All arguments were cautiously verified by the post-layout simulation setup using TSMC 0.35 µm and 0.18 µm technologies under all extreme corners.

Developing a rapid prototyping environment utilizing hardware description languages (HDLs) and conventional FPGAs can help ease and conquer the difficulties caused by the complexity of asynchronous digital systems and the advance of VLSI technology recently. We proposed a design flow and a FPGA template for implementing generalized C-element (gC) style asynchronous controllers. Utilizing conventional FPGA synthesis tools, self-timed bundled-data function modules can be realized with some effort on timing validation. The proposed design flow with FPGA-based realization approach is a very effective design methodology for rapid prototyping and functionality validation. This work could be useful for the early stage of performance estimation, power reduction exploration, circuits design training, and many other applications regarded asynchronous circuits. In this paper, the proposed FPGA-based asynchronous circuit design flow, a hands-on design tutorial, a generalized C-element template, and a list of synthesized benchmark circuits are documented and discussed in detail.

This paper addresses joint estimation of the frequency and the direction-of-arrival (DOA), under the relaxed condition that both snapshots in the temporal domain and sensors in the spacial domain are sparsely spaced. Specifically, a novel coprime sparse array allowing a large range for interelement spacings is employed in the proposed joint scheme, which greatly alleviates the conventional array's half-wavelength constraint. Further, by incorporating small-sized DFT spectrum correction with the closed-form robust Chinese Remainder Theorem (CRT), both spectral aliasing and integer phase ambiguity caused by spatio-temporal under-sampling can be removed in an efficient way. As a result, these two parameters can be efficiently estimated by reusing the observation data collected in parallel at different undersampling rates, which remarkably improves the data utilization. Numerical results demonstrate that the proposed joint scheme is highly accurate.

In this letter, we adopt a new factor analysis of neighborhood-preserving embedding (NPE) for speaker verification. NPE aims at preserving the local neighborhood structure on the data and defines a low-dimensional speaker space called neighborhood-preserving embedding space. We compare the proposed method with the state-of-the-art total variability approach on the telephone-telephone core condition of the NIST 2008 Speaker Recognition Evaluation (SRE) dataset. The experimental results indicate that the proposed NPE method outperforms the total variability approach, providing up to 24% relative improvement.