PD-SOI (Partial Depleted Silicon On Insulator) process is a good candidate technology for space system designs, since it features excellent insulation to the silicon substrate compared to the conventional bulk CMOS process. However, the radioactive particles from the low earth orbit can causes single event transient (SET) or abrupt charge collection in a circuit node, leading to a logical error in space systems. Also, the side effects such as the history effect and the kink effect in PD-SOI technology cause the threshold voltage variation, degrading the circuit performance. We propose SET-tolerant PD-SOI CMOS logic circuits using a novel active body-bias scheme. Simulation results show that the proposed circuits are more effective to SET and the side effects as well.

Parameter variations in nanometer process technology are one of the major design challenges. They cause delay to be increased on the critical path and may change the logic level of internal nodes. The basic concept to solve these problems at the circuit level, design-for-variability (DFV), is to add an error handling circuit to the conventional circuits so that they are robust to nanometer related variations. The state-of-the-art variation-aware flip flops are mainly evolved from aggressive dynamic voltage and frequency scaling (DVFS) -based low-power application systems which handle errors due to the scaled supply voltage. However, they only detect the timing errors and cannot correct the errors. We propose a variation-aware flip flop which can detect and correct the timing error efficiently. The experimental results show that the proposed variation-aware flip flop is more robust and lower power than the existing approaches.