Advanced nanometer circuits are susceptible to errors caused by process, voltage, and temperature (PVT) variations or due to a single event upset (SEU). State-of-the-art design-for-variability (DFV)-aware flip-flops (FFs) suffer from their area and timing overheads. By utilizing C-element modules, two types of FFs are proposed for error detection and error correction.

Parameter variations in nanometer process technology are one of the major design challenges. They cause delay to be increased on the critical path and may change the logic level of internal nodes. The basic concept to solve these problems at the circuit level, design-for-variability (DFV), is to add an error handling circuit to the conventional circuits so that they are robust to nanometer related variations. The state-of-the-art variation-aware flip flops are mainly evolved from aggressive dynamic voltage and frequency scaling (DVFS) -based low-power application systems which handle errors due to the scaled supply voltage. However, they only detect the timing errors and cannot correct the errors. We propose a variation-aware flip flop which can detect and correct the timing error efficiently. The experimental results show that the proposed variation-aware flip flop is more robust and lower power than the existing approaches.