This paper proposes a small 1/4Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F2 size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.

A two-dimensional (2-D) physical model of n-channel poly-Si LDD TFTs in comparison with that of SD TFTs is presented to analyze hot-carrier degradation. The model is based on 2-D device simulator's Gaussian doping profiles for the source and drain junctions fitted to the lateral and vertical impurity profiles in poly-Si obtained from a 2-D process simulator. We have shown that, in the current saturation bias (Vg

New gate logics, standby/active mode logic and , for future 1 G/4 Gb DRAM's and battery operated memories are proposed. The circuits realize sub-1-V supply voltage operation with a small 1-µA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic is composed of logic gates using dual threshold voltate (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic.

The electrical properties of thin-film SOI (silicon-on-insulator) MOSFETs, revealed by two-dimensional device simulation and experiments using electron-beam recrystallized SOI films, are reviewed and their technological perspectives are discussed. It is shown that thin-film SOI devices have a number of advantages along with some disadvantages. Carrier confinement by an interlayer SiO2 enhanced the influence of the gate electrode on the channel potential, thereby realized a high punchthrough resistance, making impurity doping into the SOI films unnecessary. The subthreshold slope factor exhibited a nearly ideal behavior, although it was somewhat degraded in the short channel region due to a two-dimensional capacitance coupling between the channel and the source or the drain. A very small capacitive-coupling between the channel and the silicon substrate made the vertical electric field extremely small, bringing about a significant increase in carrier mobility. The kink effect was confirmed to disappear due to an elevated SOI potential, which prevented impact-ionized holes from accumulating in the SOI body. The drain-current overshoot was found to be improved drastically, indicating that excess holes quickly recombine with electrons after gate turn-on, bringing about a stabilized SOI potential. However, the drain breakdown voltage had a tendency to decrease with SOI thinning, which proved to be due to an increase in the electric field at the drain. CMOS ring oscillators made with 2 µm design rule operated approximately three times faster than bulk counterparts at room temperature. It is predicted that thin-film SOI MOSFETs will have a better scalability than bulk MOSFETs not only because of their high punchthrough resistance, but because of a number of additional advantages, such as ease in device isolation as well as shallow junction formation, no impurity-induced problems, and possibility of a different scaling scenario from that in bulk devices, and so on. It is concluded that, despite some technological barries, thin-film SOI MOSFETs can offer quite a viable alternative to bulk MOSFETs as high density ULSIs, while achieving very high speed.