A Unique word-line voltage control method for the 64-Mb DRAM and beyond, which realizes a constant lifetime for thin gate oxide, is proposed. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps constant time-dependent dielectric breakdown (TDDB) lifetime, under any conditions concerning gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 105 times reliability improvement, or a 0.3 1.8-V larger word-line voltage margin to write ONE data into the cell.

A chain ferroelectric random-access memory (chain FeRAM) is a solution for future high-density and high-speed nonvolatile memory. One memory cell consists of one transistor and one ferroelectric capacitor connected in parallel, and one memory cell block consists of plural cells and a block selecting transistor in series. This configuration realizes small memory cell of 4F2 size and fast random access time. This paper shows an overview and trend of chain FeRAM architecture. First, the concept of chain FeRAM is presented, and basic operations including two cell-plate driving schemes are discussed. Second, assuming multi-megabit generation, ideal features and performances are discussed in terms of die size, speed and other aspects. Third, the prototype of chain FeRAM and the practical cell structure for megabit-scale memories using 0.5 µ m 2-metal CMOS process are demonstrated. By introducing fast and compact cell-plate drive technique, this prototype achieves random access time of 37-ns and read/write cycle time of 80-ns, which are the fastest speeds reported for FeRAMs. Fourth, after discussing future memory cell trend and problems respecting scaled FeRAMs, a gain cell block approach for future gigabit-scale chain FeRAMs is introduced. This realizes both a small average cell size and a large cell signal even at small cell polarization.

A new memory cell arrangement for a gigabit-scale NAND DRAM is proposed. Although the conventional NAND DRAM in which memory cells are connected in series realizes the small die size, it faces a crucial array noise problem in the 1 gigabit generation and beyond because of its inherent noise of the open bitline arrangement. By introducing the new cell arrangement to a NAND DRAM, the folded bitline scheme is realized, resulting in good noise immunity. The basic operation of the proposed folded bitline scheme was successfully verified using the 64 kbit test chip. The die size of the proposed NAND DRAM with the folded bitline scheme (F-NAND DRAM) at the 1 Gbit generation is reduced to 63% of that of the conventional 1 Gbit DRAM with the folded bitline scheme, assuming the bitlines and the wordlines are fabricated with the same pitch. The new 4/4 bitline grouping scheme in which cell data are read out to four neighboring bitlines is also introduced to reduce the bitline-to-bitline coupling noise to half of that of the conventional folded bitline scheme. The array noise of the proposed F-NAND DRAM with the 4/4 bitline grouping scheme at 1 Gbit generation is reduced to 10% of the read-out signal, while that of the conventional NAND DRAM with open bitline scheme is 29%, and that of the conventional DRAM with the folded bitline scheme is 22%.

This paper proposes a small 1/4Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F2 size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.

New gate logics, standby/active mode logic and , for future 1 G/4 Gb DRAM's and battery operated memories are proposed. The circuits realize sub-1-V supply voltage operation with a small 1-µA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic is composed of logic gates using dual threshold voltate (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic.

An open/folded bit-line (BL) arrangement for scaled DRAM's is proposed. This BL arrangement offers small die size and good array noise immunity. In this arrangement, one BL of an open BL pair is placed in between a folded BL pair, and the sense amplifiers (SA's) for open BL's and those for folded BL's are placed alternately between the memory arrays. This arrangement features a small 6F2 memory cell where F is the device feature size, and a relaxed SA pitch of 6F. The die size of a 64-Mb DRAM can be reduced to 81.6% compared with the one using the conventional folded BL arrangement. The BL-BL coupling noise is reduced to one-half of that of the conventional folded BL arrangement, thanks to the shield effect. Two new circuit techniques, 1) a multiplexer for connecting BL's to SA's, and 2) a binary-to-ternary code converter for the multiplexer have been developed to realize the new BL arrangement.

In order to achieve 3.3-V 1-Gb DRAM and beyond, this paper proposes a new on-chip supply voltage conversion scheme, which converts 3.3-V external supply voltage Vext to lowered 1.5-V internal supply voltage Vint without any power loss within the voltage converter. This scheme connects two identical DRAM circuits in series between Vext and Vss. By operations of two DRAM circuits with the same clock timing, the voltage between two DRAM's, Vint, is automatically fixed to 1/2Vext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2Vext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAM's. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty.