Word-Line Architecture for Highly Reliable 64-Mb DRAM

Daisaburo TAKASHIMA; Yukihito OOWAKI; Ryu OGIWARA; Yohji WATANABE; Kenji TSUCHIDA; Masako OHTA; Hiroaki NAKANO; Shigeyoshi WATANABE; Kazunori OHUCHI

Word-Line Architecture for Highly Reliable 64-Mb DRAM

Daisaburo TAKASHIMA, Yukihito OOWAKI, Ryu OGIWARA, Yohji WATANABE, Kenji TSUCHIDA, Masako OHTA, Hiroaki NAKANO, Shigeyoshi WATANABE, Kazunori OHUCHI

Full Text Views

0

Cite this

Summary :

A Unique word-line voltage control method for the 64-Mb DRAM and beyond, which realizes a constant lifetime for thin gate oxide, is proposed. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps constant time-dependent dielectric breakdown (TDDB) lifetime, under any conditions concerning gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10⁵ times reliability improvement, or a 0.3 1.8-V larger word-line voltage margin to write ONE data into the cell.

Publication: IEICE TRANSACTIONS on Electronics Vol.E75-C No.4 pp.501-507

Publication Date: 1992/04/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)

Category

Authors

Daisaburo TAKASHIMA
Yukihito OOWAKI
Ryu OGIWARA
Yohji WATANABE
Kenji TSUCHIDA
Masako OHTA
Hiroaki NAKANO
Shigeyoshi WATANABE
Kazunori OHUCHI

Keyword

Cite this

Copy

Daisaburo TAKASHIMA, Yukihito OOWAKI, Ryu OGIWARA, Yohji WATANABE, Kenji TSUCHIDA, Masako OHTA, Hiroaki NAKANO, Shigeyoshi WATANABE, Kazunori OHUCHI, "Word-Line Architecture for Highly Reliable 64-Mb DRAM" in IEICE TRANSACTIONS on Electronics, vol. E75-C, no. 4, pp. 501-507, April 1992, doi: .
Abstract: A Unique word-line voltage control method for the 64-Mb DRAM and beyond, which realizes a constant lifetime for thin gate oxide, is proposed. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps constant time-dependent dielectric breakdown (TDDB) lifetime, under any conditions concerning gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10⁵ times reliability improvement, or a 0.3 1.8-V larger word-line voltage margin to write ONE data into the cell.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_4_501/_p

Copy

@ARTICLE{e75-c_4_501,
author={Daisaburo TAKASHIMA, Yukihito OOWAKI, Ryu OGIWARA, Yohji WATANABE, Kenji TSUCHIDA, Masako OHTA, Hiroaki NAKANO, Shigeyoshi WATANABE, Kazunori OHUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Word-Line Architecture for Highly Reliable 64-Mb DRAM},
year={1992},
volume={E75-C},
number={4},
pages={501-507},
abstract={A Unique word-line voltage control method for the 64-Mb DRAM and beyond, which realizes a constant lifetime for thin gate oxide, is proposed. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps constant time-dependent dielectric breakdown (TDDB) lifetime, under any conditions concerning gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10⁵ times reliability improvement, or a 0.3 1.8-V larger word-line voltage margin to write ONE data into the cell.},
keywords={},
doi={},
ISSN={},
month={April},}

Copy

TY - JOUR
TI - Word-Line Architecture for Highly Reliable 64-Mb DRAM
T2 - IEICE TRANSACTIONS on Electronics
SP - 501
EP - 507
AU - Daisaburo TAKASHIMA
AU - Yukihito OOWAKI
AU - Ryu OGIWARA
AU - Yohji WATANABE
AU - Kenji TSUCHIDA
AU - Masako OHTA
AU - Hiroaki NAKANO
AU - Shigeyoshi WATANABE
AU - Kazunori OHUCHI
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1992
AB - A Unique word-line voltage control method for the 64-Mb DRAM and beyond, which realizes a constant lifetime for thin gate oxide, is proposed. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps constant time-dependent dielectric breakdown (TDDB) lifetime, under any conditions concerning gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10⁵ times reliability improvement, or a 0.3 1.8-V larger word-line voltage margin to write ONE data into the cell.
ER -