Open/Folded Bit-Line Arrangement for Ultra-High-Density DRAM's

Daisaburo TAKASHIMA; Shigeyoshi WATANABE; Hiroaki NAKANO; Yukihito OOWAKI; Kazunori OHUCHI

Open/Folded Bit-Line Arrangement for Ultra-High-Density DRAM's

Daisaburo TAKASHIMA, Shigeyoshi WATANABE, Hiroaki NAKANO, Yukihito OOWAKI, Kazunori OHUCHI

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An open/folded bit-line (BL) arrangement for scaled DRAM's is proposed. This BL arrangement offers small die size and good array noise immunity. In this arrangement, one BL of an open BL pair is placed in between a folded BL pair, and the sense amplifiers (SA's) for open BL's and those for folded BL's are placed alternately between the memory arrays. This arrangement features a small 6F² memory cell where F is the device feature size, and a relaxed SA pitch of 6F. The die size of a 64-Mb DRAM can be reduced to 81.6% compared with the one using the conventional folded BL arrangement. The BL-BL coupling noise is reduced to one-half of that of the conventional folded BL arrangement, thanks to the shield effect. Two new circuit techniques, 1) a multiplexer for connecting BL's to SA's, and 2) a binary-to-ternary code converter for the multiplexer have been developed to realize the new BL arrangement.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.869-872

Publication Date: 1994/05/25

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Type of Manuscript: Special Section LETTER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

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Daisaburo TAKASHIMA
Shigeyoshi WATANABE
Hiroaki NAKANO
Yukihito OOWAKI
Kazunori OHUCHI

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Daisaburo TAKASHIMA, Shigeyoshi WATANABE, Hiroaki NAKANO, Yukihito OOWAKI, Kazunori OHUCHI, "Open/Folded Bit-Line Arrangement for Ultra-High-Density DRAM's" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 5, pp. 869-872, May 1994, doi: .
Abstract: An open/folded bit-line (BL) arrangement for scaled DRAM's is proposed. This BL arrangement offers small die size and good array noise immunity. In this arrangement, one BL of an open BL pair is placed in between a folded BL pair, and the sense amplifiers (SA's) for open BL's and those for folded BL's are placed alternately between the memory arrays. This arrangement features a small 6F² memory cell where F is the device feature size, and a relaxed SA pitch of 6F. The die size of a 64-Mb DRAM can be reduced to 81.6% compared with the one using the conventional folded BL arrangement. The BL-BL coupling noise is reduced to one-half of that of the conventional folded BL arrangement, thanks to the shield effect. Two new circuit techniques, 1) a multiplexer for connecting BL's to SA's, and 2) a binary-to-ternary code converter for the multiplexer have been developed to realize the new BL arrangement.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_5_869/_p

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@ARTICLE{e77-c_5_869,
author={Daisaburo TAKASHIMA, Shigeyoshi WATANABE, Hiroaki NAKANO, Yukihito OOWAKI, Kazunori OHUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Open/Folded Bit-Line Arrangement for Ultra-High-Density DRAM's},
year={1994},
volume={E77-C},
number={5},
pages={869-872},
abstract={An open/folded bit-line (BL) arrangement for scaled DRAM's is proposed. This BL arrangement offers small die size and good array noise immunity. In this arrangement, one BL of an open BL pair is placed in between a folded BL pair, and the sense amplifiers (SA's) for open BL's and those for folded BL's are placed alternately between the memory arrays. This arrangement features a small 6F² memory cell where F is the device feature size, and a relaxed SA pitch of 6F. The die size of a 64-Mb DRAM can be reduced to 81.6% compared with the one using the conventional folded BL arrangement. The BL-BL coupling noise is reduced to one-half of that of the conventional folded BL arrangement, thanks to the shield effect. Two new circuit techniques, 1) a multiplexer for connecting BL's to SA's, and 2) a binary-to-ternary code converter for the multiplexer have been developed to realize the new BL arrangement.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - Open/Folded Bit-Line Arrangement for Ultra-High-Density DRAM's
T2 - IEICE TRANSACTIONS on Electronics
SP - 869
EP - 872
AU - Daisaburo TAKASHIMA
AU - Shigeyoshi WATANABE
AU - Hiroaki NAKANO
AU - Yukihito OOWAKI
AU - Kazunori OHUCHI
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1994
AB - An open/folded bit-line (BL) arrangement for scaled DRAM's is proposed. This BL arrangement offers small die size and good array noise immunity. In this arrangement, one BL of an open BL pair is placed in between a folded BL pair, and the sense amplifiers (SA's) for open BL's and those for folded BL's are placed alternately between the memory arrays. This arrangement features a small 6F² memory cell where F is the device feature size, and a relaxed SA pitch of 6F. The die size of a 64-Mb DRAM can be reduced to 81.6% compared with the one using the conventional folded BL arrangement. The BL-BL coupling noise is reduced to one-half of that of the conventional folded BL arrangement, thanks to the shield effect. Two new circuit techniques, 1) a multiplexer for connecting BL's to SA's, and 2) a binary-to-ternary code converter for the multiplexer have been developed to realize the new BL arrangement.
ER -