The electrical properties of thin-film SOI (silicon-on-insulator) MOSFETs, revealed by two-dimensional device simulation and experiments using electron-beam recrystallized SOI films, are reviewed and their technological perspectives are discussed. It is shown that thin-film SOI devices have a number of advantages along with some disadvantages. Carrier confinement by an interlayer SiO2 enhanced the influence of the gate electrode on the channel potential, thereby realized a high punchthrough resistance, making impurity doping into the SOI films unnecessary. The subthreshold slope factor exhibited a nearly ideal behavior, although it was somewhat degraded in the short channel region due to a two-dimensional capacitance coupling between the channel and the source or the drain. A very small capacitive-coupling between the channel and the silicon substrate made the vertical electric field extremely small, bringing about a significant increase in carrier mobility. The kink effect was confirmed to disappear due to an elevated SOI potential, which prevented impact-ionized holes from accumulating in the SOI body. The drain-current overshoot was found to be improved drastically, indicating that excess holes quickly recombine with electrons after gate turn-on, bringing about a stabilized SOI potential. However, the drain breakdown voltage had a tendency to decrease with SOI thinning, which proved to be due to an increase in the electric field at the drain. CMOS ring oscillators made with 2 µm design rule operated approximately three times faster than bulk counterparts at room temperature. It is predicted that thin-film SOI MOSFETs will have a better scalability than bulk MOSFETs not only because of their high punchthrough resistance, but because of a number of additional advantages, such as ease in device isolation as well as shallow junction formation, no impurity-induced problems, and possibility of a different scaling scenario from that in bulk devices, and so on. It is concluded that, despite some technological barries, thin-film SOI MOSFETs can offer quite a viable alternative to bulk MOSFETs as high density ULSIs, while achieving very high speed.

This paper describes a newly developed triangular mesh device simulator, TRIMEDES. TRIMEDES is merged into a supervised simulation system which covers the range from pattern layout to topography/process simulation and also to device simulation. TRIMEDES features an automatic triangular mesh generation capability, and a liking method between a topography/process simulator and a device simulator. The procedure employed in the triangular mesh generation involves the following techniques; (1) primary mesh generation, (2) feedback rate method in order to achieve smooth element size variation, and (3) relaxation technique after mesh generation to suppress obtuse triangles. This procedure proves to be effective and robust in the mesh generation for nonplanar device structures. In order to link the device simulator TRIMEDES to the topograhpy/process simulator, the device shape is represented as closed-loop string topography data and a triangular mesh is generated based on the string data. The pre-processor of the mesh generator has been developed, which rearranges the string data to cope with the mesh generation. The geometrical shape of a device can be reflected in the device simulation, since the string shape data of the topography/process simulation are smoothly transferred to the device simulator.

Design concepts and backgrounds of a 3-dimensional semiconductor process simulator are presented. It is designed to become a basis of developing semiconductor process models. An input language is designed to realize flexibly controlling simulation sequence, and its interpreter program is designed to accept external software to be controlled and to be integrated into a system. To realize data-exchanges between the process simulator and other software, a self-describing data-file format is designed and related program libraries are developed. A C++ class for solving drift-diffusion type partial-differential-equation in a three-dimensional space is developed.

We investigated the impact of velocity overshoot effect on collector signal delay of bipolar devices by using Monte Carlo simulation method. We found that insertion of an i-layer (lightly doped, intrinsic layer) between base and collector can increase the delay, but the strength of this effect is a function of the i-layer thickness. When the i-layer becomes thinner, the problem of increasing delay seems to disappear. This recovery of delay is realised with a mechanism which is completely different from that in drift-diffusion model.

Efficient device simulation methods to realize circuit level analyses have been proposed. Highly conductive wire regions, the current source, and lumped elements such as resistances and capacitances can be handled within the framework of a present device simulation software. Additionally, the simulation area can be reduced and computational efforts can be saved by adopting the inner Neumann boundary condition between devices which affect each other very little except through the wire region. The regularity of the coefficient matrix can be preserved in all cases, so it is possible to get stability of matrix solver and save computer memory. The advantage of matrix regularity is enhanced to speed up when using a vector-concurrent computer. Hence, the computational cost can be saved considerably. These numerical techniques have been implemented in the authors' device simulation software.

This letter describes the newly developed device simulator TRITON. Emphasis is on the fully automatic triangle mesh generation, based on the string data which represent the device shape. Poisson's and current continuity equations for electrons and holes are discretized by the control volume method.