The electrical properties of thin-film SOI (silicon-on-insulator) MOSFETs, revealed by two-dimensional device simulation and experiments using electron-beam recrystallized SOI films, are reviewed and their technological perspectives are discussed. It is shown that thin-film SOI devices have a number of advantages along with some disadvantages. Carrier confinement by an interlayer SiO2 enhanced the influence of the gate electrode on the channel potential, thereby realized a high punchthrough resistance, making impurity doping into the SOI films unnecessary. The subthreshold slope factor exhibited a nearly ideal behavior, although it was somewhat degraded in the short channel region due to a two-dimensional capacitance coupling between the channel and the source or the drain. A very small capacitive-coupling between the channel and the silicon substrate made the vertical electric field extremely small, bringing about a significant increase in carrier mobility. The kink effect was confirmed to disappear due to an elevated SOI potential, which prevented impact-ionized holes from accumulating in the SOI body. The drain-current overshoot was found to be improved drastically, indicating that excess holes quickly recombine with electrons after gate turn-on, bringing about a stabilized SOI potential. However, the drain breakdown voltage had a tendency to decrease with SOI thinning, which proved to be due to an increase in the electric field at the drain. CMOS ring oscillators made with 2 µm design rule operated approximately three times faster than bulk counterparts at room temperature. It is predicted that thin-film SOI MOSFETs will have a better scalability than bulk MOSFETs not only because of their high punchthrough resistance, but because of a number of additional advantages, such as ease in device isolation as well as shallow junction formation, no impurity-induced problems, and possibility of a different scaling scenario from that in bulk devices, and so on. It is concluded that, despite some technological barries, thin-film SOI MOSFETs can offer quite a viable alternative to bulk MOSFETs as high density ULSIs, while achieving very high speed.
Makoto YOSHIMI
Minoru TAKAHASHI
Shigeru KAMBAYASHI
Masato KEMMOCHI
Hiroaki HAZAMA
Tetsunori WADA
Koichi KATO
Hiroyuki TANGO
Kenji NATORI
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Makoto YOSHIMI, Minoru TAKAHASHI, Shigeru KAMBAYASHI, Masato KEMMOCHI, Hiroaki HAZAMA, Tetsunori WADA, Koichi KATO, Hiroyuki TANGO, Kenji NATORI, "Electrical Properties and Technological Perspectives of Thin-Film SOI MOSFETs" in IEICE TRANSACTIONS on Electronics,
vol. E74-C, no. 2, pp. 337-351, February 1991, doi: .
Abstract: The electrical properties of thin-film SOI (silicon-on-insulator) MOSFETs, revealed by two-dimensional device simulation and experiments using electron-beam recrystallized SOI films, are reviewed and their technological perspectives are discussed. It is shown that thin-film SOI devices have a number of advantages along with some disadvantages. Carrier confinement by an interlayer SiO2 enhanced the influence of the gate electrode on the channel potential, thereby realized a high punchthrough resistance, making impurity doping into the SOI films unnecessary. The subthreshold slope factor exhibited a nearly ideal behavior, although it was somewhat degraded in the short channel region due to a two-dimensional capacitance coupling between the channel and the source or the drain. A very small capacitive-coupling between the channel and the silicon substrate made the vertical electric field extremely small, bringing about a significant increase in carrier mobility. The kink effect was confirmed to disappear due to an elevated SOI potential, which prevented impact-ionized holes from accumulating in the SOI body. The drain-current overshoot was found to be improved drastically, indicating that excess holes quickly recombine with electrons after gate turn-on, bringing about a stabilized SOI potential. However, the drain breakdown voltage had a tendency to decrease with SOI thinning, which proved to be due to an increase in the electric field at the drain. CMOS ring oscillators made with 2 µm design rule operated approximately three times faster than bulk counterparts at room temperature. It is predicted that thin-film SOI MOSFETs will have a better scalability than bulk MOSFETs not only because of their high punchthrough resistance, but because of a number of additional advantages, such as ease in device isolation as well as shallow junction formation, no impurity-induced problems, and possibility of a different scaling scenario from that in bulk devices, and so on. It is concluded that, despite some technological barries, thin-film SOI MOSFETs can offer quite a viable alternative to bulk MOSFETs as high density ULSIs, while achieving very high speed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e74-c_2_337/_p
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@ARTICLE{e74-c_2_337,
author={Makoto YOSHIMI, Minoru TAKAHASHI, Shigeru KAMBAYASHI, Masato KEMMOCHI, Hiroaki HAZAMA, Tetsunori WADA, Koichi KATO, Hiroyuki TANGO, Kenji NATORI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Electrical Properties and Technological Perspectives of Thin-Film SOI MOSFETs},
year={1991},
volume={E74-C},
number={2},
pages={337-351},
abstract={The electrical properties of thin-film SOI (silicon-on-insulator) MOSFETs, revealed by two-dimensional device simulation and experiments using electron-beam recrystallized SOI films, are reviewed and their technological perspectives are discussed. It is shown that thin-film SOI devices have a number of advantages along with some disadvantages. Carrier confinement by an interlayer SiO2 enhanced the influence of the gate electrode on the channel potential, thereby realized a high punchthrough resistance, making impurity doping into the SOI films unnecessary. The subthreshold slope factor exhibited a nearly ideal behavior, although it was somewhat degraded in the short channel region due to a two-dimensional capacitance coupling between the channel and the source or the drain. A very small capacitive-coupling between the channel and the silicon substrate made the vertical electric field extremely small, bringing about a significant increase in carrier mobility. The kink effect was confirmed to disappear due to an elevated SOI potential, which prevented impact-ionized holes from accumulating in the SOI body. The drain-current overshoot was found to be improved drastically, indicating that excess holes quickly recombine with electrons after gate turn-on, bringing about a stabilized SOI potential. However, the drain breakdown voltage had a tendency to decrease with SOI thinning, which proved to be due to an increase in the electric field at the drain. CMOS ring oscillators made with 2 µm design rule operated approximately three times faster than bulk counterparts at room temperature. It is predicted that thin-film SOI MOSFETs will have a better scalability than bulk MOSFETs not only because of their high punchthrough resistance, but because of a number of additional advantages, such as ease in device isolation as well as shallow junction formation, no impurity-induced problems, and possibility of a different scaling scenario from that in bulk devices, and so on. It is concluded that, despite some technological barries, thin-film SOI MOSFETs can offer quite a viable alternative to bulk MOSFETs as high density ULSIs, while achieving very high speed.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - Electrical Properties and Technological Perspectives of Thin-Film SOI MOSFETs
T2 - IEICE TRANSACTIONS on Electronics
SP - 337
EP - 351
AU - Makoto YOSHIMI
AU - Minoru TAKAHASHI
AU - Shigeru KAMBAYASHI
AU - Masato KEMMOCHI
AU - Hiroaki HAZAMA
AU - Tetsunori WADA
AU - Koichi KATO
AU - Hiroyuki TANGO
AU - Kenji NATORI
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 1991
AB - The electrical properties of thin-film SOI (silicon-on-insulator) MOSFETs, revealed by two-dimensional device simulation and experiments using electron-beam recrystallized SOI films, are reviewed and their technological perspectives are discussed. It is shown that thin-film SOI devices have a number of advantages along with some disadvantages. Carrier confinement by an interlayer SiO2 enhanced the influence of the gate electrode on the channel potential, thereby realized a high punchthrough resistance, making impurity doping into the SOI films unnecessary. The subthreshold slope factor exhibited a nearly ideal behavior, although it was somewhat degraded in the short channel region due to a two-dimensional capacitance coupling between the channel and the source or the drain. A very small capacitive-coupling between the channel and the silicon substrate made the vertical electric field extremely small, bringing about a significant increase in carrier mobility. The kink effect was confirmed to disappear due to an elevated SOI potential, which prevented impact-ionized holes from accumulating in the SOI body. The drain-current overshoot was found to be improved drastically, indicating that excess holes quickly recombine with electrons after gate turn-on, bringing about a stabilized SOI potential. However, the drain breakdown voltage had a tendency to decrease with SOI thinning, which proved to be due to an increase in the electric field at the drain. CMOS ring oscillators made with 2 µm design rule operated approximately three times faster than bulk counterparts at room temperature. It is predicted that thin-film SOI MOSFETs will have a better scalability than bulk MOSFETs not only because of their high punchthrough resistance, but because of a number of additional advantages, such as ease in device isolation as well as shallow junction formation, no impurity-induced problems, and possibility of a different scaling scenario from that in bulk devices, and so on. It is concluded that, despite some technological barries, thin-film SOI MOSFETs can offer quite a viable alternative to bulk MOSFETs as high density ULSIs, while achieving very high speed.
ER -