Design of a Two-Dimensional Digital Chaos Circuit Realizing a Henon Map
Summary :
An econominal implementation of a chaos circuit onto the hardware is an important subject. In this letter, a two-dimensional digital chaos circuit realizing a Henon map is designed. Concerning the attractor and the bifurcation diagram of the proposed circuit, numerical simulations are performed to confirm the validity of the circuit algorithm. Furthermore, the proposed digital chaos circuit is designed by Verilog-HDL (Hardware Description Language). The proposed digital chaos circuit can be implemented into the form of the FPGA (Field Programmable Gate Array).
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E81-C No.1 pp.78-81
- Publication Date
- 1998/01/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Category
- Electronic Circuits
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Kei EGUCHI, Takahiro INOUE, Akio TSUNEDA, "Design of a Two-Dimensional Digital Chaos Circuit Realizing a Henon Map" in IEICE TRANSACTIONS on Electronics,
vol. E81-C, no. 1, pp. 78-81, January 1998, doi: .
Abstract: An econominal implementation of a chaos circuit onto the hardware is an important subject. In this letter, a two-dimensional digital chaos circuit realizing a Henon map is designed. Concerning the attractor and the bifurcation diagram of the proposed circuit, numerical simulations are performed to confirm the validity of the circuit algorithm. Furthermore, the proposed digital chaos circuit is designed by Verilog-HDL (Hardware Description Language). The proposed digital chaos circuit can be implemented into the form of the FPGA (Field Programmable Gate Array).
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e81-c_1_78/_p
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@ARTICLE{e81-c_1_78,
author={Kei EGUCHI, Takahiro INOUE, Akio TSUNEDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a Two-Dimensional Digital Chaos Circuit Realizing a Henon Map},
year={1998},
volume={E81-C},
number={1},
pages={78-81},
abstract={An econominal implementation of a chaos circuit onto the hardware is an important subject. In this letter, a two-dimensional digital chaos circuit realizing a Henon map is designed. Concerning the attractor and the bifurcation diagram of the proposed circuit, numerical simulations are performed to confirm the validity of the circuit algorithm. Furthermore, the proposed digital chaos circuit is designed by Verilog-HDL (Hardware Description Language). The proposed digital chaos circuit can be implemented into the form of the FPGA (Field Programmable Gate Array).},
keywords={},
doi={},
ISSN={},
month={January},}
Copy
TY - JOUR
TI - Design of a Two-Dimensional Digital Chaos Circuit Realizing a Henon Map
T2 - IEICE TRANSACTIONS on Electronics
SP - 78
EP - 81
AU - Kei EGUCHI
AU - Takahiro INOUE
AU - Akio TSUNEDA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 1998
AB - An econominal implementation of a chaos circuit onto the hardware is an important subject. In this letter, a two-dimensional digital chaos circuit realizing a Henon map is designed. Concerning the attractor and the bifurcation diagram of the proposed circuit, numerical simulations are performed to confirm the validity of the circuit algorithm. Furthermore, the proposed digital chaos circuit is designed by Verilog-HDL (Hardware Description Language). The proposed digital chaos circuit can be implemented into the form of the FPGA (Field Programmable Gate Array).
ER -
English
