In this study, multimode chaos observed from two coupled chaotic oscillators with hard nonlinearities is investigated. At first, a simple chaotic oscillator with hard nonlinearities is realized. It is confirmed that in this chaotic oscillator the origin is always asymptotically stable and that the solution, which is excited by giving relatively large initial conditions, undergoes period-doubling bifurcations and bifurcates to chaos. Next, the coexistence of four different modes of oscillations are observed from two coupled chaotic oscillators with hard nonlinearities by both of circuit experiments and computer calculations. One of the modes of oscillation is a nonresonant double-mode oscillation and this oscillation is stably generated even in the case that oscillation is chaotic. Namely, for this oscillation mode, chaotic oscillation and periodic oscillation can be simultaneously excited. This phenomenon has not been reported yet, and we name this phenomenon as double-mode chaos. Finally, the beat frequency of the double-mode chaos is confirmed to be changed by varying the value of the coupling capacitor.

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great dfficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.

In this letter, a novel current-mode operational amplifier (COA) is proposed. The proposed COA can operate at 2 V (1 V) supply voltage. For high frequency operation it has only an npn transistor in signal path. Finally, SPICE simulation are shown to verify the performance of the proposed COA.

The objective, when mapping a wafer, is to capture the the full variation across the wafer while minimising the number of measurements. This is a very similar objective to that of experimental design and this paper applies classical Design Of Experiment (DOE) techniques to the selection of measurement points for wafer mapping. The resulting measurements are then fitted using Response Surface Methodology (RSM) from which contour plots or wafer maps can be generated. The accuracy of the fit can be ascertained by inspection of the adjusted R2 value and it is demonstrated that in many cases transformations can be used to improve the accuracy of the resulting wafer maps.

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 µm device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.

This paper proposes a photonic integrated beam forming and steering network (BFN) that uses switched true-time-delay (TTD) silica-based waveguide circuits for phased array antennas. The TTD-BFN has thermooptic switches and variable time delay lines. This TTD-BFN controls four array elements, and can form and steer a beam. An RF test was carried out in the 2.5 GHz microwave frequency range. The experimental results show a peak-to-peak phase error of 6.0 degrees and peak-to-peak amplitude error of 2.0 dB. Array factors obtained from the measured results agree well with the designed ones. This silica-based beam former will be a key element in phased array antennas.

This paper describes ALINX (Advanced Low-voltage Interface Circuit System), a low-power and high-speed interface circuit of submicron CMOS LSI for digital information and telecommunications systems. Differential and single-ended ALINXs are low-voltage swing I/O interface circuits with less than 1.0 V swing from a 1.2 V supply. Specifically, the differential ALINX features a pair of complementary NMOS push-pull drivers operating from a 1.2 V supply, reducing power consumption compared to conventional high-speed interface circuits operating from a 5 V or 3.3 V supply. The DC power consumption is approximately 11% of ECL. We observed 622 Mbps differential transmission with 8 mW power consumption and single-ended transmission at 311 Mbps with 14 mW with a PN23 pseudo-random pattern. We also describe a noise characteristic and ALINX applications to high-speed data buses and LSI for telecommunications systems. A time/space switch LSI with 0.9 W total power consumption was fabricated by 0.5 µm CMOS process technology. This chip can use a plastic QFP.

In circuit partitioning for FPGAs, partitioned signal nets are connected using I/O blocks, through which signals are coming from or going to external pins. However, the number of I/O blocks per chip is relatively small compared with the number of logic-blocks, which realize logic functions, accommodated in the FPGA chip. Because of the I/O block limitation, the size of a circuit implemented on each FPGA chip is usually small, which leads to a serious decrease of logic-block utilization. It is required to utilize unused logic-blocks in terms of reducing the number of I/O blocks and realize circuits on given FPGA chips. In this paper, we propose an algorithm which partitions an initial circuit into multi-FPGA chips. The algorithm is based on recursive bi-partitioning of a circuit. In each bi-partitioning, it searches a partitioning position of a circuit such that each of partitioned subcircuits is accommodated in each FPGA chip with making the number of signal nets between chips as small as possible. Such bi-partitioning is achieved by computing a minimum cut repeatedly applying a network flow technique, and replicating logic-blocks appropriately. Since a set of logic-blocks assigned to each chip is computed separately, logic-blocks to be replicated are naturally determined. This means that the algorithm makes good use of unused logic-blocks from the viewpoint of reducing the number of signal nets between chips, i.e. the number of required I/O blocks. The algorithm has been implemented and applied to MCNC PARTITIONING 93 benchmark circuits. The experimental results demonstrate that it decreases the maximum number of I/O blocks per chip by a maximum of 49% compared with conventional algorithms.

An automatic transistor-level performance fault tracing method is proposed which is applicable to the case where only CAD layout data is available in the CAD-linked electron beam test system. The technique uses an integrated algorithm that combines a previously proposed transistor-level fault tracing algorithm and a successive circuit extraction from CAD layout data. An expansion of the algorithm to the fault tracing in a combined focused ion beam and electron beam test system which enables us to measure signals on the interconnections in the lower layers is also described. An application of the technique to a CMOS model layout with about 100 transistors shows its validity.

In this paper, an approach to derive a logic function of asynchronous circuits from a graph-based model called Signal Transition Graphs (STG) is discussed. STG's are Petri nets, whose transitions are interpreted as a signal transition on the circuit inputs or gate outputs, and its marking represents a binary state of the circuit. STG's can represent a behavior of circuit, to derive logic functions, however, the reachability graph should be constructed. In the verification of STG's some method based on Occurrence nets (OCN) and its prefix, called unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating substate space of a given STG using the structural properties of OCN. The proposed method can be seem as a parallel algorithm for deriving a logic function.

To evaluate the radial eigenmode field distributions and the resonance wavelengths of axially symmetric pillbox resonator, a numerical method is described which is based on the FE-BPM expression in cylindrical coordinates. Under the weakly guiding approximation, we solve Fresnel equation and can get a fairly accurate result. By using effective index method, 3-D pillbox guiding structure is reduced to 2-D one which is then used for the analysis. One advantage of this method is that it is applicable for the axially symmetric optical waveguides with arbitrary index distribution. The validity of this method is checked by comparing the results of this method with those of the analytical ones. This method is applied for the evaluation of the coupling properties of a coupled structure consisting of a pillbox resonator and a curved waveguide placed outside the pillbox. This coupled structure has a good prospect to be used as optical wavelength filter. By varying the separation distance between the pillbox and the outer curved waveguide, the power transfer due to coupling is determined near the resonance wavelength 0.9 µm.

A fully-differential switched-current (SI) circuit provided with clock-feedthrough (CFT) and common mode rejection and offset compensation schemes is described. Different from a conventional SI memory cell, it takes the difference between two differential inputs to deliver the balanced differential currents. Transistor level simulations and error analyses are given to demonstrate its performance.

This paper describes an MOS charge-mode version of a T-Model neural-based PCM encoder. The neural-based PCM encoding networks are designed, simulated and implemented using MOS charge-mode circuits. Simulation results are given for both the T-Model and the Hopfield model CMOS charge-mode PCM encoders, and demonstrate the T-Model neural-based one performs the PCM encoding perfectly, while the Hopfield one fails to.

In this paper, the diffusion parameter-values in the K+-ion diffused waveguides made by diluted KNO3 with NaNO3 in the soda-lime glass, which are determined from measured values of the effective index, are presented together with a simple method for the determination. The surface-index changes are measured for the waveguides by KNO3 melts with 75%-, 50%- and 30%-dilutions (weight ratio), and for comparison purpose, also by the pure KNO3, and the dependence of the index-profile on the dilution of KNO3 in the ion-source melt is shown. Change of the two-dimensional index profile in the diffused channel waveguide with the KNO3-dilution is also shown, which is calculated with the measured diffusion parameters.

We propose an equivalent circuit model described by the Rössler equation. Then we can consider a coupled Rössler system with a physical meaning on the connection. We consider an oscillatory circuit such that two identical Rössler circuits are coupled by a resistor. We have studied three routes to entirely and almost synchronized chaotic attractors from phase-locked periodic oscillations. Moreover, to simplify understanding of synchronization phenomena in the coupled Rössler system, we investigate a mutually coupled map that shows analogous locking properties to the coupled Rössler System.

In this paper, a new switched-current auto-tuning filter is proposed. Switched-current (SI) is a current-mode analog sampled-data circuit technique. An SI circuit can be realized using only standard digital CMOS technologies, and is capable of realizing high frequency circuits. The proposed filter is composed of SI-OTA (operational transconductance amplifier) integrators. The gain of an SI-OTA integrator can be electronically controlled by the bias current. The proposed filter is a current controlled filter (CCF) and a PLL technique was used as its tuning method. A 2nd-order SI auto-tuning low-pass filter with 100kHz cutoff frequency was designed assuming a 2µm CMOS process. The characteristics of this SI filter and its tuning characteristics were confirmed by SPICE simulations.

This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.

We have developed a 15-Gbit/s 96-gate Si-bipolar gate array using 0.5-µm Si-bipolar technology, a sophisticated internal cell design, an I/O buffer design suitable for high-speed operation and high-frequency package technology. The decision circuit and 4 : 1 multiplexer fabricated on the gate array operate up to 15-Gbit/s and above 10-Gbit/s respectively. The data input sensitivity and the phase margin of the decision circuit are 53 mVpp and 288 at 10-Gbit/s operation. This gate array promises to be useful in shortening the development period and lowering cost of 10-Gbit/s class IC's.

In this paper, we discuss computational methods for obtaining the bifurcation points and the branch directions at branching points of solution curves for the nonlinear resistive circuits. There are many kinds of the bifurcation points such as limit point, branch point and isolated point. At these points, the Jacobian matrix of circuit equation becomes singular so that we cannot directly apply the usual numerical techniques such as Newton-Raphson method. Therefore, we propose a simple modification technique such that the Newton-Raphson method can be also applied to the modified equations. On the other hand, a curve tracing algorithm can continuously trace the solution curves having the limit points and/or branching points. In this case, we can see whether the curve has passed through a bifurcation point or not by checking the sign of determinant of the Jacobian matrix. We also propose two different methods for calculating the directions of branches at branching point. Combining these algorithms, complicated solution curves will be easily traced by the curve tracing method. We show the example of a Hopfield network in Sect.5.

Tracing solution curves of nonlinear equations is an important problem in circuit simulation. In this paper, simple techniques are proposed for improving the computational efficiency of the spherical method, which is a method for tracing solution curves. These techniques are very effective in circuit simulation where solution curves often turn very rapidly. Moreover, they can be easily performed with little computational effort.