This paper describes, from a system architectural viewpoint, how knowledge-based technologies have been utilized in developing EXLOG (an LSI circuit synthesis system) and SOFTEX (a software synthesis system) inside the authors' projects. Although the system architectures for EXLOG and SOFTEX started from the same production systems, consisting of transformation rules in the middle of the 1980's, both branched off in different directions in the 1990's. Based on experiences with EXLOG and SOFTEX, the differences between LSI and software design models are discussed, and the future directions are indicated for the knowledge-based design system architectures.

Tracing solution curves of nonlinear equations is an important problem in circuit simulation. In this paper, simple techniques are proposed for improving the computational efficiency of the spherical method, which is a method for tracing solution curves. These techniques are very effective in circuit simulation where solution curves often turn very rapidly. Moreover, they can be easily performed with little computational effort.

In this paper, we presented an analysis of single and coupled microstrip lines covered with protective dielectric film which is usually used in the microwave integrated circuits. The method employed in the characterization is called partial-boundary element method (p-BEM). The p-BEM provides an efficient means to the analysis of the structures with multilayered media or covered with protective dielectric film. The numerical results show that by changing the thickness of the protective dielectric films such as SiO2, Si and Polyimide covered on these lines on a GaAs substrate, the coupled microstrip lines vary within 10% on the characteristic impedance and within 25% on the effective dielectric constant for the odd mode of coupled microstrip line, respectively, in comparison with the structures without the protective dielectric film. In contrast, the single microstrip lines vary within 4% on the characteristic impedance and within 8% on the effective dielectric constant, respectively. The protective dielectric film affects the odd mode of the coupled lines more strongly than the even mode and the characteristics of the single microstrip lines.

Interdigital transducers (IDTs) with leaky-SAWs propagating on 36 YX-LiTaO3, and 41 and 64 YX-LiNbO3 were theoretically analyzed, providing a new equivalent circuit. This equivalent circuit included attenuation constant due to leakage as well as conductance caused by bulkwave radiation. All circuit parameters were derived by solving integral equations. Fundamental experiments showed fairly good agreement between theoretical and experimental results, which gave very accurate design tools for leaky-SAW devices.

This paper deals with a high-speed digital circuit for discrete cosine transform (DCT). We propose a new algorithm that reduces the number of calculations for partial sum-of-products in the DCT and synthesize the small gate depth circuit of DCT by using carry-propagation-free adders based on redundant binary {1,0,1} representation. The gate depth is only half to one third that of the conventional algorithms with the same number of gates.

This paper described discrete time Cellular Neural Networks (DT-CNN) with two types of neuron circuits for image coding from an analog format to a digital format and their VLSI implementations. The image coding methods proposed in this paper have been investigated for a purpose of transmission of a coded image and restoration again without a large loss of an original image information. Each neuron circuti of a network receives one pixel of an input image, and processes it with binary outputs data fed from neighboring neuron circuits. Parallel dynamics quantization methods have been adopted for image coding methods. They are performed in networks to decide an output binary value of each neuron circuit according to output values of neighboring neuron circuits. Delayed binary outputs of neuron circuits in a neighborhood are directly connected to inputs of a current active neuron circuit. Next state of a network is computed form a current state at some neuron circuits in any time interval. Models of two types of neuron circuits and networks are presented and simulated to confirm an ability of proposed methods. Also, physical layout designs of coding chips have been done to show their possibility of VLSI realizations.

A new mm-wave IC, constructed by flip-chip bonded heterojunction transistors and microstrip lines formed on Si substrate, has been proposed and demonstrated by using MBB (micro bump boding) technology. Millimeter-wave characteristics of the MBB region has been estimated by electro-magnetic field analysis. Good agreements between calculated and measured characteristics of this new IC (named MFIC: millimeter-wave flip-chip IC) have been obtained up to 60 GHz band. Several MFIC amplifiers with their designed performances have been successfully fabricated.

The goal of this paper is to propose a new symbolic model checking approach named time-space modal model checking, which could be applicable to verification of bit-slice microprocessor of infinite bit width and one dimensional systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.

This paper deals with the problems in testing large mixed-signal ICs. To help generating test patterns of these larger mixed-signal circuits for a functional test, a fast fault simulation algorithm and a fault model voltage stuck-at fault" which the algorithm is based on, are proposed. A voltage stuck-at fault is that a signal line sticks its voltage level at a certain constant. Under an assumption that blocks in a circuit are designed as identically current-independent, i.e. their input impedance can be regarded as infinite and their output impedance as zero, fault simulation can be realized by the event driven method and the concurrent method and can detect voltage stuck-at faults. These methods are essential for digital fault simulation and very effective to high speed simulation, although they were impossible for an analog or mixed-signal circuit by a conventional algorithm. Furthermore, the efficiency of the simulation is improved because I/O relation of blocks is approximated to a stepwise linear function. The above techniques and methods make fault simulation for a mixed-signal circuit possible in practical use. Actually, a fault simulator was implemented, then some test circuits were simulated. The simulator is really faster than conventional simulation based on circuit simulation. Next, fault analysis was applied to several bipolar ICs to verify the validity of the fault model voltage stuck-at faults". Analyses of open and short faults between terminals of transistors and resistors show that this fault model has sufficient coverage (more than 50%) to test mixed-signal circuit.

This paper presents the concept of k-FR circuits. The controllability of such a circuit is high due to its special structure. It is shown that all stuck-at faults and stuck-open faults in a k-FR circuit can be detected and located by k(k1)1 test vectors under the highly observable condition which assumes the output of every gate to be observable. k is usually two or three. This paper also presents an algorithm for converting an arbitrary combinational circuit into a k-FR circuit. A k-FR circuit is easy to test when using technologies such as the electron-beam probing, the current measurement, or the CrossCheck testability solution.

Current testing has been proposed as an alternative technique for testing fully CMOS digital LSIs. Current testing has higher fault coverage than conventional stuck-at fault (SAF) testing and is more economical because it detects a wide range of faults and requires fewer test vectors than does SAF testing. We have proposed a current testing that measures the integral of the power supply current (IDD) during one clock period including the switching current. Since this method cannot be affected by the switching current, it can be used to test an LSI operating at a relatively high clock freuqnecy. This paper presents an improved current testing method for CMOS digital and analog LSIs. The method uses two current values (i.e., an upper limit and a lower limit) and judges the circuit under test to be faulty if the measured IDD is outside these limits. The proposed current testing is evaluated here for some kinds of faults (e.g., the bridging fault and the breaking fault) in digital and mixed-signal LSIs, and its efficiency of the current testing using SPICE3.

A method to design one-dimensional cellular arrays to be used as TPG circuits of BIST is described. The interconnections between cells are not limited to adjacent ones but allowed to some neighbors. Completely regular structures that have full-transition coverages for every k-dimensional subspace of state variables are first shown. Then, almost regular arrays which can operate on maximum cycles are derived based on fast parallel implementations of LFSRs.

A single bridging fault location technique for CMOS combinational circuits is proposed. In this technique, the cause of an error observed at the primary outputs in deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is [the number of gates][the number of tests]2 bits, which is much smaller than that of the fault dictionary. The experimental results show that the number of possible bridging faults is reduced to less than 5 in several seconds, when using the tests to detect single stuck-at faults and considering only the bridging faults between physically adjacent nets.

There is general trend toward larger chip size and tighter layout due to customer requests of loading more and more functions on single chip. This trend makes yield difficult to be maintained high enough, since larger amount of defects are distributed on such large and tight-ruled chips. To overcome such a situation, RADLYS (RAnDom Logic Yield Simulator) and DD-TEG (Defect Density TEG) have been developed. DD-TEG extracts defect size distribution and its amount automatically, while RADLYS simulates defects on any layout and outputs yield based on the extracted defect size distribution. Critical layout from yield point of view can be found in this procedure. DD-TEG and RADLYS are used as a set of parameter extraction and simulation of the SPICE. In this paper, we introduce these tools and showed two application results. The predicted yield showed a good agreement with the actual yield in the first application (Optical Device A). Critical layout at the Local I/O portion was found in the second application (Random Logic portion of Memory Device B) and the layout was changed based on the RADLYS results.

Some undetectable stuck-at faults called the redundant faults are included in practical combinational circuits. The redundant fault does not affect the functional behavior of the circuit even if it exists. The redundant fault, however, causes undesirable effects to the circuit such as increase of delay time and decrease of testability of the circuit. It is considered that some redundant faults may cause the logical defects in the future. In this paper, firstly, we study the testability of the redundant fault in the combinational circuit by using delay effects. Secondly, we propose a method for generating a test-pair of a redundant fault by using an extended seven-valued calculus, called TGRF (Test-pair Generation for Redundant Fault). TGRF generates a dynamically sensitizable path for the target line which propagates the change in the value on the target line to a primary output. Finally, we show experimental results on the benchmark circuits under the assumptions of the unit delay and the fanout weighted delay models. It shows that test-pairs for some redundant faults are generated theoretically.

This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate a test generation procedure previously proposed and reduce the number of test vectors generated, while higher fault coverage is derived. The first technique proposed in this paper, which is applied at the first phase of test generation, is rules of ordering vector pairs to be analyzed, to derive high fault coverage without repeating the analysis for the same vector pairs. The second one is to generate new vector pairs for undetected faults, instead of random vector pairs. Both techniques are based on the idea that faults close to primary inputs should be detected earlier than close to primary outputs. The third technique proposed here is how to construct vector pairs from one input vector in order to accelerate test generation especially for circuits with many primary inputs and scan flip-flops. Experimental results for bench-mark circuits show the effectiveness of the techniques.

This paper presents a performance analysis of the standard non-coherent delay-locked loop in asynchronous direct-sequence code division multiple access (DS-CDMA) environments. In particular, the effects of multiple access interference on the loop performance are addressed. We work out an expression for the steady-state tracking-error variance and provide performance curves in terms of mean time to lose lock as a function of the number of interfering users and Eb/No.

In this study, a ring of simple chaotic circuits coupled by inductors is investigated. An extremely simple three-dimensional autonomous circuit is considered as a chaotic subcircuit. By carrying out circuit experiments and computer calculations for two, three or four subcircuits case, various synchronization phenomena of chaos are confirmed to be stably generated. For the three subcircuits case, two different synchronization modes coexist, namely in-phase synchronization mode and three-phase synchronization mode. By investigating Poincar map, we can see that two types of synchronizations bifurcate to quasi-synchronized chaos via different bifurcation route, namely in-phase synchronization undergoes period-doubling route while three-phase synchronization undergoes torus breakdown. Further, we investigate the effect of the values of coupling inductors to bifurcation phenomena of two types of synchronizations.

Switched-capacitor chaotic neurons fabricated in a full-custom integrated circuit are used to investigate the behavior of 2- and 3-neuron chaotic neural networks. Various sets of parameters are used to visualize the dynamical responses of the networks. Hysteresis of the network is also demonstrated. Lyapunov exponents are approximated from the measured data to characterize the state of each neuron. The effect of the finite length of data and the rounding effect of data acquisition system to the computation of Lyapunov exponents are briefly discussed.

The state of the art of low-voltage (LV) analog circuit design techniques is reviewed, and fundamental design techniques are identified and classified as follows: 1) current-mode, 2) series-to-parallel, 3) signal range sharing, 4) dynamic bias, 5) linear bias, and 6) LV regulator. A relatively wide variety of low frequency application circuits have been developed, but future development is expected for wide-bandwidth application circuits such as a voltage-controlled-oscillator (VCO), a balanced multiplier, etc. The circuit techniques such as current-mode, signal range sharing, and dynamic bias will probably be most important for advanced future circuit designs.