Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis
Summary :
This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate a test generation procedure previously proposed and reduce the number of test vectors generated, while higher fault coverage is derived. The first technique proposed in this paper, which is applied at the first phase of test generation, is rules of ordering vector pairs to be analyzed, to derive high fault coverage without repeating the analysis for the same vector pairs. The second one is to generate new vector pairs for undetected faults, instead of random vector pairs. Both techniques are based on the idea that faults close to primary inputs should be detected earlier than close to primary outputs. The third technique proposed here is how to construct vector pairs from one input vector in order to accelerate test generation especially for circuits with many primary inputs and scan flip-flops. Experimental results for bench-mark circuits show the effectiveness of the techniques.
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- IEICE TRANSACTIONS on Information Vol.E78-D No.7 pp.811-816
- Publication Date
- 1995/07/25
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- Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
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Seiji KAJIHARA, Rikiya NISHIGAYA, Tetsuji SUMIOKA, Kozo KINOSHITA, "Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis" in IEICE TRANSACTIONS on Information,
vol. E78-D, no. 7, pp. 811-816, July 1995, doi: .
Abstract: This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate a test generation procedure previously proposed and reduce the number of test vectors generated, while higher fault coverage is derived. The first technique proposed in this paper, which is applied at the first phase of test generation, is rules of ordering vector pairs to be analyzed, to derive high fault coverage without repeating the analysis for the same vector pairs. The second one is to generate new vector pairs for undetected faults, instead of random vector pairs. Both techniques are based on the idea that faults close to primary inputs should be detected earlier than close to primary outputs. The third technique proposed here is how to construct vector pairs from one input vector in order to accelerate test generation especially for circuits with many primary inputs and scan flip-flops. Experimental results for bench-mark circuits show the effectiveness of the techniques.
URL: https://global.ieice.org/en_transactions/information/10.1587/e78-d_7_811/_p
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@ARTICLE{e78-d_7_811,
author={Seiji KAJIHARA, Rikiya NISHIGAYA, Tetsuji SUMIOKA, Kozo KINOSHITA, },
journal={IEICE TRANSACTIONS on Information},
title={Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis},
year={1995},
volume={E78-D},
number={7},
pages={811-816},
abstract={This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate a test generation procedure previously proposed and reduce the number of test vectors generated, while higher fault coverage is derived. The first technique proposed in this paper, which is applied at the first phase of test generation, is rules of ordering vector pairs to be analyzed, to derive high fault coverage without repeating the analysis for the same vector pairs. The second one is to generate new vector pairs for undetected faults, instead of random vector pairs. Both techniques are based on the idea that faults close to primary inputs should be detected earlier than close to primary outputs. The third technique proposed here is how to construct vector pairs from one input vector in order to accelerate test generation especially for circuits with many primary inputs and scan flip-flops. Experimental results for bench-mark circuits show the effectiveness of the techniques.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis
T2 - IEICE TRANSACTIONS on Information
SP - 811
EP - 816
AU - Seiji KAJIHARA
AU - Rikiya NISHIGAYA
AU - Tetsuji SUMIOKA
AU - Kozo KINOSHITA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E78-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 1995
AB - This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate a test generation procedure previously proposed and reduce the number of test vectors generated, while higher fault coverage is derived. The first technique proposed in this paper, which is applied at the first phase of test generation, is rules of ordering vector pairs to be analyzed, to derive high fault coverage without repeating the analysis for the same vector pairs. The second one is to generate new vector pairs for undetected faults, instead of random vector pairs. Both techniques are based on the idea that faults close to primary inputs should be detected earlier than close to primary outputs. The third technique proposed here is how to construct vector pairs from one input vector in order to accelerate test generation especially for circuits with many primary inputs and scan flip-flops. Experimental results for bench-mark circuits show the effectiveness of the techniques.
ER -
English
