We propose a directly controlled emitter-follower circuit with a feedback type level stabilizer for low-voltage, low-power and high-speed bipolar ECL circuits. The emitter-follower circuit employs a current source structure that compensates speed and power for various supply voltage and temperature. The feedback controlled circuit with a small current source stabilizes 'High' level. At a power consumption of 1 mW/gate, the new circuit is 45% faster under the loaded condition (FO1, CL0.5 pF) and has 47% better load driving capability than conventional ECL gates.

A 10-kW (53V/200A), forced-air-cooled DC-DC converter has been developed for fuel cell systems. This converter uses new high-voltage bipolar-mode static induction transistors (BSIT), a new driving method, a zero-voltage-switched pulse-width-modulation technique, and a new litz wire with low AC resistance. It weighs only 16.5kg, has a volume of 26,000cm3, operates at 40kHz, and has a power conversion efficiency of about 95%. The power loss of this converter is 20% less than that of conventional natural-air-cooled DC-DC converters, and the power density is 3 times as high.

The recent progress of B-ISDN signaling systems has enabled networks to handle calls which require a wide variety of ATM connection sets. This paper is concerned with the circuit group which handles calls requesting asymmetric forward and backward multi-connections, and has the capability of both bandwidth negotiation and bandwidth reservation as a traffic control for enhancing call blocking performance. A model of the circuit group is first established focusing on the call level characteristics of the group, and then a method based on the reduced load approximation and an approximate analysis of a multirate group is proposed for calculating approximate blocking probabilities. The accuracy of the approximation method is evaluated numerically by comparing with an exact method and simulation. Further the impact of bandwidth negotiation and reservation on call blockings is examined based on numerical examples.

We report the first monolithic integration of InGaAs/InAlAs resonant tunneling diode (RTD) and high electron mobility transistor (HEMT) epitaxially grown on an InP substrate. The transconductance for a 1-µm gate HEMT was 430 mS/mm and the peak-to-valley current ratio of the RTD was 5.1. Using the integrated structure, we demonstrate basic digital circuits to show low power characteristics of an RTD-load inverter and a static RAM cell circuit, consisting of a single transistor with two RTDs on the transistor. The memory cell circuit exhibits bistability, based on the RTD's negative differential resistance (NDR), at supply voltages from 0.6 to 1.1 V. The static power consumption was 7.3 µW/gate for the inverter and 3.0 µW for memory cell.

Circuit access control is a traffic control technique of rejecting calls arriving at a group of specified circuits to make the group free at a target scheduled time so that the capacity may be dynamically reallocated to serve other traffic demand. This technique plays an important role for resource allocation control in state-of-the-art capacity reconfigurable networks as well as for switching calls on a reserved basis in the ISDNs. In this paper, we present a novel adaptive scheme for circuit access control in order to overcome the inefficiency of the conventional deterministic scheme. The presented scheme is based only on knowledge about service time and bandwidth characteristics of calls. The transitional behavior of the circuit group under the scheme is analyzed, and the gain in utilization achieved by the adaptive scheme is examined. We treat a model of the circuit group shared by multi-slot calls with different service times, and describe the results of the transient analysis and the approximation method for evaluating the gains.

In this paper, we demonstrate how Yamakawa's chaotic chips and Chua's circuits can be used to implement a secure communication system. Furthermore, their performance for the secure communication is discussed.

B-ISDN telecommunication systems will require signal processing speeds up to 600 Mbps or more. We must therefore consider the affects of signal reflection, signal attenuation, time dalay, and so on when designing these systems. The higher the signal speed, the larger the electrical noise induced around the connector, especially in the plated through holes (PTHs) area. This paper presents the results of our investigation focused on connector mounting configurations in the signal transmission line, especially whether or not signals transmit through the PTH in a printed circuit board (PCB). How the signal reflection characteristics depend upon transmission line configurations are discussed and experimental results and simulation analyses for a transmission line system using a small miniature A-type (SMA) connector as an example are performed. It is suggested that designs for future high-speed signal transmission circuits take into account the PTH diameter and/or the PTH pitch conditions, values for which can be determined from simulation analysis.

This paper discusses a CMOS differential-difference amplifier circuit suitable for low voltage operation. A new multiple weighted input transconductor circuit structure is suggested to be use in DDA implementation. The proposed DDA can be employed in several analog/digital systems to improve their parameters. Selected examples of the proposed transconductor/DDA applications are also discussed.

In this paper, we describe a worst-case design optimization approach for statistical design of integrated circuits with a circuit performance model scheme. After formulating worst-case optimization to an unconstrained multi-objective function minimization problem, a new objective function is proposed to find an optimal point. Then, based on an interpolation model scheme of approximating circuit performance, realistic worst-case analysis can be easily done by Monte Carlo based method without increasing much the computational load. The effectiveness of the presented approach is demonstrated by a standard test function and a practical circuit design example.

This paper presents 1V supply voltage Bi-CMOS current mode circuits. The circuits are consist of current mirrors, current comparators and current sources. The circuits have some advantages such as high accuracy, high speed, high density and low power supply. As an application of the circuits, an analog-to-digital converter (ADC) is given. The ADC operates with small chip area and low power dissipation. The performances of the proposed circuits were confirmed by using SPICE2 simulation.

An efficient algorithm is given for finding all solutions of piecewise-linear resistive circuits containing nonseparable transistor models such as the Gummel-Poon model or the Shichman-Hodges model. The proposed algorithm is simple and can be easily programmed using recursive functions.

The efficiency of a guided-probe fault location process is affected by the number of the probed lines. This number depends on the size of the target area and the method by which a line is selected for probing. This paper presents a method for reducing the size of the target area in a sequential circuit by introducing the concepts of Type- and Type- faults. This paper also presents a method of selecting lines for probing in a more efficient way. The efficiency of the proposed methods is demonstrated by experimental results.

It has become very important to study the lightning surges that were induced in subscriber telecommunication equipment because of the increase of susceptible circuits to the over voltage. The test generator is desire to be developed evaluating the resistibility of equipments against lightning surges. This paper proposes a new lightning-test method for subscriber telecommunication equipment. The waveform of the test generator simulates that of the induced lightning surge voltage caused by a nearby return stroke. The output impedance of the surge generator is determined to match the common-mode impedance of telecommunication lines. The damaged condition of circuit parts and the trouble occurrence rate estimated by using this method agree well with actual observations.

This paper describes an efficient slew rate enhancement technique especially suitable for an operational amplifier used in an LCD driver IC. This technique employs an input-dependent biasing without directly monitoring an input; instead, monitoring an output of the first stage of the amplifier. This enhancement technique is easily applied to a conventional two-stage operational amplifier and requires only 8 additional transistors to increase slew rates for both rising and falling edges. The bias currents of the first and the second stages are simultaneously controlled by this biasing. Experimental operational amplifiers with and without this enhancement have been fabricated to demonstrate the improvement of slew rate. Slew rates of 12.5V/µsec for the rising edge and 50V/µsec for the falling edge with a 100 pF load capacitance have been achieved by this technique, compared with slew rates of 0.3V/µsec for the rising edge and 5V/µsec for the falling edge in the conventional amplifier.

This paper proposes a constructive linearization method for transistor circuits based on a polynomial representation of nonlinear transfer functions. The nonlinear transfer functions for various configurations have been shown in a polynomial form. Then the results have been applied to several bipolar transistor circuits to exemplify the proposed designing method.

Concerned is a spectral profile of electromagnetic (EM) emission from a signal line on a high-speed digital circuit. The authors have proposed and examined an a priori method to predict the peak frequencies on spectral profile of EM emission from printed circuit boards (PCBs). Profile of an EM spectrum is determined by the resonance of digital circuits. It is the purpose of this paper to investigate the parameters that determine the spectral profile of EM emission from a signal line on a PCS. In this paper, measurements and calculations of EM spectra were carried out for different load capacitances. EM emissions were measured with a small loop antenna at a 50mm from the surface of the PCB. Measured EM spectra had two peaks. Calculated EM spectra, which was based on transient current given by the analog simulator SPICE, had two peaks too. Results of calculations of EM spectra for different internal capacitances of an IC tell that lower peak frequency is determined by the resonance frequency of the resonant loop which is composed of an IC package and a decoupling capacitor. Comparison with measured EM spectra and calculated EM spectra for different load resistances tell that sharpness of the other peak depends on Q factor of a resonant loop which includes a signal line. Therefore the peak frequencies of EM emission spectrum can be predicted as two resonance frequencies of two resonant circuits.

A system for measuring the low frequency amplitude and phase noises was set-up, with employing a phase sensitive detector and phase-shifter. It is noted that both noises were partly correlated. The phase noise was explained by the transit time fluctuation due to the fluctuating diffusion coefficient. The amplitude noise reduction was demonstrated by applying the inverted output of the phase noise to the amplitude noise.

This paper proposes the overlapped block relaxation Newton method for greatly reducing the number of iterations needed for simulating large scale nonlinear circuits. The circuit is partitioned into subcircuits, i.e., overlapped blocks consisting of core nodes and overlapped nodes. The core nodes form the core circuit for each overlapped block and the overlapped nodes form the overlapped circuit. The Newton-Raphson method is applied to all overlapped blocks independently and the approximation vector for relaxation is determined by node voltages of core nodes. An overlapped circuit is considered to be the representative circuit of the outside circuit for the core circuit. Therefore, the accuracy of the approximation vector for relaxation may be improved and the number of relaxation steps may be greatly reduced. Core nodes are determined automatically by reflecting the circuit structure, then the overlapping level is determined automatically. We show that this method has good performance for simulating large scale circuits, and that it is faster than the nonlinear direct method which is used in standard circuit simulators.

A negation-limited circuit is a combinational circuit which includes at most [log(n1)] NOT gates. We show a relationship between the size of negation-limited circuits computing clique functions and the number of NOT gates in the circuits.

We developed a parallel bordered-block-diagonal (BBD) matrix solution for parallel circuit simulation. In parallel circuit sumulation on a MIMD parallel computer, a circuit is partitioned into as many subcircuits as the processors of a parallel computer. Circuit partition produce a BBD matrix. In parallel BBD matrix solution, diagonal blocks are easily solved separately in each processor. It is difficult, however, to solve the interconnection (IC) submatrix of a BBD matrix effectively in parallel. To make matters worse, the more a circuit is partitioned into subcircuits for highly parallel circuit simulation, the larger the size of an IC submatrix becomes. From an examination, we found that an IC submatrix is more dense (about 30% of all entries are non-zeros) than a normal circuit matrix, and the non-zeros per row in an IC submatrix are almost constant with the number of subcircuits. To attain high-speed circuit simulation, we devised a data structure for BBD matrix processing and an approach to parallel BBD matrix solution. Our approach solves the IC submatrix in a BBD matrix as well as the diagonal blocks in parallel using all processors. In this approach, we allocate an IC submatrix in block-wise order rather than in dot-wise order onto all processors. Thus, we balance the processor perfomance with the communication capacity of a parallel computer system. When we changed the block size of IC submatrix allocation from dot-wise order to 88 block-wise order, the 88 block-wise order allocation almost halved the matrix solution time. The parallel simulation of a sample circuit with 3277 transistors was 16.6 times faster than a single processor when we used 49 processors.