OTA (Operational Transconductance Amplifier) is a useful circuit in analog signal processing systems, especially in high-frequency applications. Important features of OTA are: infinite input impedance, electrically changeable transconductance (Gm), and much wider operation range without negative feedback such as in OPamp applications. The good linearity of OTA over wide input range is necessary to extend the application fields of OTA. Several techniques are developed to extend the input range with good linearity. In this paper, a highly-linear CMOS-OTA operating under 1 V power supply, is proposed. The concept of the proposed OTA is based on class-AB operation of two n-channel MOSFETs in the saturation region. By improving the input stage circuits, wide input range can be achieved. SPICE simulations are performed to verify the performance of the proposed OTA.

Photonic ATM switching systems with Terabit/s throughput are desirable for future broadband ISDN systems. Since electronic LSI-based ATM switching systems are planned to have the throughput of 160Gb/s, a photonic ATM switching system should take the role of the highest layer in a hybrid switching network which includes electronic LSI-based ATM switching systems as its sub-system. This report discusses the state-of-the-art photonic devices needed for a frequency-self-routing ATM photonic switching system with maximum throughput of 5Tb/s. This kind of systems seems to be a moderate system for the first phase photonic switching system with no insuperable obstacle for initiating development, even though none of the devices and technologies required have yet been developed to meet the specifications. On the contrary, for realizing further enlarged throughput as the second-phase photonic switching system, there are huge fundamental research projects still remaining for establishing the technology utilizing the spectrum broadened over 120nm and highly-dense FDM technologies based on homodyne coherent detection, if supposing a simple architecture. "Ultra devices" seem to be the photonic devices based on new tailored materials of which gain and refractive index are designed to realize ultra-wide spectrum utilization.

The increasing size and complexity of integrated circuits has lead to the development of advanced algorithms and techniques for circuit simulation. The majority of circuit simulators rely on the Newton-Raphson algorithm for the solution of nonlinear equations that arise from the circuit description. Unfortunately, a good estimate of the root to be found is needed for the algorithm to converge. The convergence rate of the algorithm is quadratic once the method gets "close enough" to the solution, but before reaching this point the method may follow a complex route through unrealistic values of the circuit variables, leading eventually to divergence. Simulations performed with SPICE on several test circuits reveal that during the first iterations of the Newton-Raphson algorithm internal node voltages exceed the power supply voltage of several orders of magnitudes even for simple circuits. A new simulation program called MUSIC (Multilevel Simulator for Integrated Circuits) has been developed to overcome these drawbacks. In MUSIC the circuit to be simulated is decomposed in subcircuits, which may contain instances of other subcircuits up to any nesting level. Subcircuits are then simulated independently with a multilevel Newton algorithm permitting to reduce both the large oscillations that circuit variables undergo during the simulation process and the number of iterations necessary for the circuit to converge. The novel feature of this multilevel algorithm is the propagation of the already calculated terminal voltages, which become known after a subcircuit has converged, to the subcircuits connected to same terminals. In this way the information regarding node voltages is propagated through the network without constraining conditions that do not have physical counterpart. Simulations performed on chains of inverters and a 4-bit full adder evidence how MUSIC is able to improve the convergence rate and to reduce the intermediate voltage spikes.

This paper presents a design of low-power CMOS OTA-C filters suitable for on-chip integration of advanced monolithic system LSIs that have analog I/O and digital signal processing capability. First, we discuss the distortion of MOS cross-coupled circuits which have a quite low distortion when the MOS FETs have the square law characteristics. Considering the nonidealities of MOS FET, however, we find that the third harmonic component of signal dominates the total harmonic distortion (THD) of the cross-coupled pair circuit. We propose a new architecture to reduce the 3rd harmonic component. Low distortion operational transconductance amplifiers (OTA) which consist of the proposed low distortion cross-coupled pair are applied to the realization of OTA-Capacitor filters. The SPICE simulation shows that the THD of the filter is 0.0047% and the power dissipation is 22.6 mW.

The consequences of energy transport related effects like velocity overshoot on the performance of bipolar transistors have already been studied previously. So far however most of the applied models were only 1D and it remained unclear whether such effects would have a significant influence on important quantities like ECL gate delay accessible only on the circuit level. To the authors' best knowledge in this paper for the first time the consequences of energy transport related effects on the circuit level are investigated in a rigorous manner by mixed level device/circuit simulation incorporating full 2D numerical hydrodynamic models on the device level.

New insights pertaining to hot-carrier degradation of CMOS inverters have been obtained using an in-house reliability simulator named HIRES (Hitachi Reliability Simulator). The simulation of three out of four different inverter configurations which utilize series-connected NMOSFET devices between the output node and ground results in higher levels if degradation than that induced by intuition. For two of the configurations--the cascode inverter (where the gate of all NMOSFET's are connected to the input) and the two-input NAND gate--degradation levels are comparable to that of a simple two-transistor CMOS inverter. This high level of degradation is found to be caused by the fact that most of the output voltage is dropped across one of the series-connected NMOSFET transistors rather than being equally divided between the two. From degradation simulation results, a design methodology is developed to optimize the inverter circuits to minimize hot-carrier degradation by balancing the degradation suffered between the two series-connected NMOSFET's. Using this approach, up to a factor of 109 improvement in device lifetime is achieved.

This paper proposes a novel method to realize highly linear MOS circuits using MOSFETs in the nonsaturation region. The proposed method is based on the cancellation of nonlinearity of two MOSFETs by using a current inversiontype negative impedance converter. First, grounded and floating resistor realizations are discussed. Next, by exploiting the MOS resistor circuits, gyrators and inductors are realized. As an application example, a third-order doubly-terminated LC filter is simulated. SPICE analysis shows low total harmonic distortions, excellent controllability and small gain error in the passband.

Two types of novel nVT level shift circuits based on the square law characteristics of MOSFETs have been proposed. These circuits generate VIN+nVT or VIN-nVT (where VT is a threshold voltage), if the input voltage is applied as the VIN. These circuits can be widely used in MOSFET characterization, compensating VT effect, VT measurement, level shifting, etc. Type 1 is directly derived from the nVT-sift circuit proposed by Wang. Type 2 can reduce a total chip area than type 1 and has a wider input range. SPICE simulations show that the proposed circuits have a very wide input range and a small power consumption.

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.

An analog approach alternative to the Hopfield method is presented for solving constrained combinatorial optimization problems. In this new method, a saddle point of a Lagrangian function is searched using a constrained dynamical system with the aid of an appropriate transformation of variables. This method always gives feasible solutions in contrast to the Hopfield scheme which often outputs infeasible solutions. The convergence of the method is proved theoretically and some effective schemes are recommended for eliminating some variables for the case we resort to numerical simulation. An analog electronic circuit is devised which implements this method. This circuit requires fewer wirings than the Hopfield networks. Furthermore this circuit dissipates little electrical power owing to subthreshold operation of MOS transistors. An annealing process, if desired, can be performed easily by gradual increase in resistance of linear resistors in contrast to the Hopfield circuit which requires the variation in the gain of amplifiers. The objective function called an energy is ensured theoretically to decrease throughout the annealing process.

The crosstalk characteristics of a long-wavelength monolithically integrated photoreceiver array are analyzed. The device consists of an array of transimpedance photoreceivers fabricated on a semi-insulating InP substrate. The distance between the photodetectors is large enough to suppress the photonic crosstalk. Therefore, the crosstalk of the device is mainly due to signal propagation from the channels through the power line shared by each channel on the chip. This crosstalk is inevitable to the photoreceiver arrays which employ common power lines. The magnitude of the crosstalk largely depends on the impedance of the power-supply circuit outside the chip. The crosstalk spectrum often has a peak and recess structure. The crosstalk peak at the edge of the operating band-width is due to the resonance characteristic of the transimpedance amplifier. The other peak and recess structures on the spectrum are due to the resonance phenomena of on-chip and off-chip capacitors and inductance on the power-supply line outside the chip. This crosstalk can be reduced by using on-chip bypass capacitance and dumping resistance. However, the resonance due to the capacitance and inductance on the power-supply circuit outside the chip can't be controlled by the on-chip components. Therefore, an optimized design for the power supply circuit outside the chip is also indispensable for suppressing crosstalk.

This paper presents an improved current-mode circuit for implementation of a chaotic neuron model. The proposed circuit uses a switched-current integrator and a nonlinear output function circuit, which is based on an operational transconductance amplifier, as building blocks. Is is shown by SPICE simulations and experiments using discrete elements that the proposed circuit well replicates the behavior of the chaotic neuron model.

Optical waveguides are one of the key devices for photonic integrated circuits considered to be one of the candidates for optical interconnects. In particular lossless bend type waveguides are necessary to integrate different optical devices monolithically. In this paper, we report on the bending loss characteristics of the multi-quantum well bend waveguide with respect to the bend radius and lateral optical mode confinement. We show that to decrease the bending loss to less than 0.5 dB, it is necessary to increase either the confinement or the bend radius. For an example, when the confinement is around 85%, the bend radius should be more than 2 mm. We also show the application of the S-bend waveguides to directional coupler type optical switch.

An efficient algorithm is presented for finding all solutions of piecewise-linear resistive circuits. In this algorithm, a simple sign test is performed to eliminate many linear regions that do not contain a solution. This makes the number of simultaneous linear equations to be solved much smaller. This test, in its original form, is applied to each linear region; but this is time-consuming because the number of linear regions is generally very large. In this paper, it is shown that the sign test can be applied to super-regions consisting of adjacent linear regions. Therefore, many linear regions are discarded at the same time, and the computational efficiency of the algorithm is substantially improved. The branch-and-bound method is used in applying the sign test to super-regions. Some numerical examples are given, and it is shown that all solutions are computed very rapidly. The proposed algorithm is simple, efficient, and can be easily programmed.

In 1963, the authors began to develop a tuning circuit (hereafter referred to as the 'circuit') consisting of an inductor, fixed capacitors and a variable capacitor. The circuit required very high accuracy and stability, and the aging influence on resonant frequency needed to be Δf/f0 0.12% for 20 years. When we started, there was no methodology available for designing such a long-term stable circuit, so we reinvestigated our previous studies concerning aging characteristics and formed a design concept. We designed the circuit by bearing in mind that an inductor was subject to natural and stress demagnetization (as indicated by disaccommodation), and assumed that a capacitor changed its characteristics linearly over a logarithmic scale of time. (This assumption was based on short-term test results derived from previous studies.) We measured the aging characteristics of the circuits at room temperature for 20 years, from 1966. The measurement results from the 20-year study revealed that the aging characteristics predicted by the design concept were reasonably accurate.

Two types of circuit architecture for GaAs LSI are described. The first circuit is named Stacked DCFL which has supply voltage compatibility with Si CMOS/BiCMOS and ECL operating on 3 V or 3.3 V. A divide by 128/129 prescaler IC has been developed to confirm the Stacked DCFL circuit operation. The second circuit is named SVFL which operates on single supply voltage by using Schottky FET characteristics in spite of normally-on FET logic. Both circuit architectures are based on the virtual ground concept. The transition time of 45 psec was obtained by the SVFL ring oscillator circuit fabricated with 1 µm gate length FET process, and the transition time of DCFL using the same process was from 80 psec to 100 psec. Stacked DCFL and SVFL are candidates for an internal gate and an input/output interface circuit for GaAs ASIC, respectively.

Four circuit techniques and a layout design scheme were proposed to realize a 2 Mb VRAM used 0.8 µm technology. They are the enhanced circuit technologies for high speed operation, the functional circuit design and the effective repair schemes for a VRAM, the low power consumption techniques to active and standby mode and a careful layout design scheme realizing high noise immunity. Using these design techniques, a 2 Mb VRAM is suitable for the graphics application of a 5125128 pixels basis screen, with a clear mode of 4.6 GByte/sec and a 4-multi column write mode of 400 MByte/sec, even using the same 0.8 µm technology as the previous VRAM (1 Mb) was realized.

The design of a high speed self-routing network switch module is described. Clock distribution and timing design to achieve high-speed operation are considered. A 88-port self-routing Benes network switch prototype on multi-chip module is fabricated using 44-port space division switch LSIs. The switch module achieves a maximum measured clock frequency of 750MHz under switching operation. Resultant total throughput of the switch module is 12Gbit/s.

We propose a high-level synthesis method that uses data path information given by a designer. The main purpose of this method is to generate a control unit, one of the most difficult aspects of hardware design. In general, designers can specify data paths easily. Therefore, we believe that basing a method on specified data path information is the best way to synthesize hardware that more closely satisfies the designer's requirements. Moreover, a datapath-constrained scheduling algorithm can perform both "scheduling" and "resource allocation" at the same time. In particular, the resource allocation explicitly decides used paths as well as functional modules in each execution state. This cannot be done with previously reported algorithms.

In this paper we present a method to generate test sequences for stuck-at faults in sequential circuits which have distinguishing sequences. Since the circuit may have no distinguishing sequence, we use two design techniques for circuits which have distinguishing sequences. One is at state transition level and the other is at gate level. In our proposed method complete test sequence can be generated. The sequence consists of test vectors for the combinational part of the circuit, distinguishing sequences and transition sequences. The test vectors, which are generated by a combinational test generator, cause faulty staes or faulty output responses for a fault, and disinguishing sequences identify the differences between faulty states and fault free states. Transition sequences are necessary to make the state in the combinational vectors. And the distinguishing sequence and the transition sequence are used in the initializing sequence. Some techniques for shortening the test sequence is also proposed. The basic ideas of the techniques are to use a short initializing sequence and to find the order in concatenating sequences. But fault simulation is conducted so as not to miss any faults. The initializing sequence is obtained by using a distinguishing sequence. The efficiency of our method is shown in the experimental results for benchmark circuits.