New Insights in Optimizing CMOS Inverter Circuits with Respect to Hot-Carrier Degradation

Peter M. LEE

New Insights in Optimizing CMOS Inverter Circuits with Respect to Hot-Carrier Degradation

Peter M. LEE

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New insights pertaining to hot-carrier degradation of CMOS inverters have been obtained using an in-house reliability simulator named HIRES (Hitachi Reliability Simulator). The simulation of three out of four different inverter configurations which utilize series-connected NMOSFET devices between the output node and ground results in higher levels if degradation than that induced by intuition. For two of the configurations--the cascode inverter (where the gate of all NMOSFET's are connected to the input) and the two-input NAND gate--degradation levels are comparable to that of a simple two-transistor CMOS inverter. This high level of degradation is found to be caused by the fact that most of the output voltage is dropped across one of the series-connected NMOSFET transistors rather than being equally divided between the two. From degradation simulation results, a design methodology is developed to optimize the inverter circuits to minimize hot-carrier degradation by balancing the degradation suffered between the two series-connected NMOSFET's. Using this approach, up to a factor of 10⁹ improvement in device lifetime is achieved.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.2 pp.194-199

Publication Date: 1994/02/25

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Type of Manuscript: Special Section PAPER (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD 93))

Category: Coupled Device & Circuit Modeling

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Peter M. LEE, "New Insights in Optimizing CMOS Inverter Circuits with Respect to Hot-Carrier Degradation" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 2, pp. 194-199, February 1994, doi: .
Abstract: New insights pertaining to hot-carrier degradation of CMOS inverters have been obtained using an in-house reliability simulator named HIRES (Hitachi Reliability Simulator). The simulation of three out of four different inverter configurations which utilize series-connected NMOSFET devices between the output node and ground results in higher levels if degradation than that induced by intuition. For two of the configurations--the cascode inverter (where the gate of all NMOSFET's are connected to the input) and the two-input NAND gate--degradation levels are comparable to that of a simple two-transistor CMOS inverter. This high level of degradation is found to be caused by the fact that most of the output voltage is dropped across one of the series-connected NMOSFET transistors rather than being equally divided between the two. From degradation simulation results, a design methodology is developed to optimize the inverter circuits to minimize hot-carrier degradation by balancing the degradation suffered between the two series-connected NMOSFET's. Using this approach, up to a factor of 10⁹ improvement in device lifetime is achieved.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_2_194/_p

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@ARTICLE{e77-c_2_194,
author={Peter M. LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={New Insights in Optimizing CMOS Inverter Circuits with Respect to Hot-Carrier Degradation},
year={1994},
volume={E77-C},
number={2},
pages={194-199},
abstract={New insights pertaining to hot-carrier degradation of CMOS inverters have been obtained using an in-house reliability simulator named HIRES (Hitachi Reliability Simulator). The simulation of three out of four different inverter configurations which utilize series-connected NMOSFET devices between the output node and ground results in higher levels if degradation than that induced by intuition. For two of the configurations--the cascode inverter (where the gate of all NMOSFET's are connected to the input) and the two-input NAND gate--degradation levels are comparable to that of a simple two-transistor CMOS inverter. This high level of degradation is found to be caused by the fact that most of the output voltage is dropped across one of the series-connected NMOSFET transistors rather than being equally divided between the two. From degradation simulation results, a design methodology is developed to optimize the inverter circuits to minimize hot-carrier degradation by balancing the degradation suffered between the two series-connected NMOSFET's. Using this approach, up to a factor of 10⁹ improvement in device lifetime is achieved.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - New Insights in Optimizing CMOS Inverter Circuits with Respect to Hot-Carrier Degradation
T2 - IEICE TRANSACTIONS on Electronics
SP - 194
EP - 199
AU - Peter M. LEE
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
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VL - E77-C
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JA - IEICE TRANSACTIONS on Electronics
Y1 - February 1994
AB - New insights pertaining to hot-carrier degradation of CMOS inverters have been obtained using an in-house reliability simulator named HIRES (Hitachi Reliability Simulator). The simulation of three out of four different inverter configurations which utilize series-connected NMOSFET devices between the output node and ground results in higher levels if degradation than that induced by intuition. For two of the configurations--the cascode inverter (where the gate of all NMOSFET's are connected to the input) and the two-input NAND gate--degradation levels are comparable to that of a simple two-transistor CMOS inverter. This high level of degradation is found to be caused by the fact that most of the output voltage is dropped across one of the series-connected NMOSFET transistors rather than being equally divided between the two. From degradation simulation results, a design methodology is developed to optimize the inverter circuits to minimize hot-carrier degradation by balancing the degradation suffered between the two series-connected NMOSFET's. Using this approach, up to a factor of 10⁹ improvement in device lifetime is achieved.
ER -