The consequences of energy transport related effects like velocity overshoot on the performance of bipolar transistors have already been studied previously. So far however most of the applied models were only 1D and it remained unclear whether such effects would have a significant influence on important quantities like ECL gate delay accessible only on the circuit level. To the authors' best knowledge in this paper for the first time the consequences of energy transport related effects on the circuit level are investigated in a rigorous manner by mixed level device/circuit simulation incorporating full 2D numerical hydrodynamic models on the device level.