Some new circuit configurations for dual-input integrators and differentiators are proposed. The use of a multiplier device around the Operational Amplifier (OA) yields electronic tunability of their time-constant (To) by a Control Voltage (Vx). Experimental results in support of theoretical design and analysis are included.

In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.

This paper describes design considerations for high frequency active BPFs up to 100 MHz. The major design issues for high frequency active filters are the excess phase shift in the integrators and high power consumption of the integrators. Typical bipolar transistor based transconductors such as the Gilbert gain cell and the linearized transconductor with two asymmetric emitter-coupled pairs have been analyzed and compared. It has been clarified that the power consumption of the linearized transconductor can be much smaller than that of the Gilbert gain cell because of its high transconductance to working current ratio while maintaining a signal to noise ratio of the same order. A simple high-speed fully differential linearized transconductor cell is proposed with emitter follower buffers and resistive loads for excess phase compensation. A novel gyrator based transformation for the LC ladder BPF has been introduced. This transformation has resulted in a structure with simple capacitor-coupled active resonators which exactly preserves the original transfer function. A fourth order 10.7 MHz BPF IC was designed using the proposed transconductors. It was fabricated and has demonstrated the usefulness of the proposed approach. In addition, an experimental 100 MHz second order BPF IC with Q=14 has been successfully implemented indicating the potential of the proposed approach.

This paper theoretically evaluates the external electro-optic (EO) sampling of high-speed electrical signals using poled polymers as materials for a proximity electric-field sensor. Based on the derivation of the half-wave voltage and the analysis of a static electric field coupled to the polymeric media placed over IC interconnections, invasiveness, voltage sensitivity, and spatial resolution have been discussed. The polymeric sensors have shown to be used in contact with the IC interconnections with negligibly small invasiveness, thus making polymeric sensors provide higher sensitivity and spatial resolution than inorganic crystals such as GaAs and KD*P.

This paper describes an automatic transistor model parameter generation technique for a circuit simulator which can take device geometry into account. An 'area factor' is used to generate model parameters for different transistor shapes; however, the conventional method could not reflect the actual geometry differences other than for the emitter area. This resulted in inaccurate model parameters and such parameters were not acceptable to accurately simulate circuits for RF ICs. The proposed technique uses actually measured parameters and process data for a reference transistor and generates the individual model parameters for different shape transistors. In this technique, the parasitic resistor values are calculated and fitted in place of directly extracting them from the measured data. This ensures a better estimate. The reference transistor is made sufficiently large to neglect measurement errors in generating the parasitic capacitors. Thus, the model parameters for a very small transistor can be generated accurately. The model generating procedure has been implemented as a pre-processor to SPICE. This technique enables a fast turn around for RF IC circuit design which uses various shape transistors.

Power-law decay of current for the application of step-function voltage observed for amorphous materials can be expressed by an admittance sa(0a1) of a linear diode using complex angular frequency s. It is shown that power-law decay can be interpreted as a superposition of exponential decays having fractally distributed relaxation times and simulated using RC networks. By use of a similar manner, admittance s-b (0b1) showing the relation of duality can be simulated using RL networks. According to these methods, we can synthesize the admittance involving non-integer exponents systematically.

Formation of thin insulating SiO2 films by anodic oxidation of silicon was studied as a part of investigating an alternative method of fabricating low-cost silicon MIS solar cells. Anodization in the constant-voltage mode was carried out in nonaqueous ethylene glycol solution. The film thickness was carefully measured using an ellipsometer of wavelength 6238 . MIS cell performance was evaluated by comparing the open circuit voltage VOC and the short circuit current density ISC with those of the bare Schottky cell (without anodization) under illumination by a tungsten lamp. It was found that anodization in the constant-voltage mode can increase VOC without reducing ISC, and that anodization in the constant-voltage mode is more controllable and reproducible. The optimun formation voltage which gives the maximum VOC of the MIS cell depends on the forming voltage of oxide. A brief discussion on the mechanism for VOC increase is given.

This paper was written for LSI engineers in order to demonstrate the effect of optical interconnections in LSIs to improve both the speed and power performances of 0.5 and 0.2 µm CMOS microprocessors. The feasibilities and problems regarding new micronsize optoelectronic devices as well as associated electronics are discussed. Actual circuit structures clocks and bus lines used for optical interconnection are discussed. Newly designed optical interconnections and the speed power performances are compared with those of the original electrical interconnection systems.

Chaotic behavior in a series resonance circuit with a ferroelectric triglycine sulfate (TGS) crystal was observed just below the ferroelectric phase transition temperature. We have analyzed the nonlinear responses by applying external electric fields to the crystal. The computer simulation was made for the modified forroelectric hysteresis loops to realize the experimental results. The fractal correlation dimension was determined to be ν=1.8 in the chaotic phase.

In complex self-checking systems several blocks (i.e. functional blocks and checkers) are embedded. In order to check the self-checking properties of such blocks we need to know the set of vectors they receive from the blocks feeding their inputs (i.e. the code word output spaces of the source blocks). In a complex system the computation of the output spaces by means of exhaustive simulation of the system is intractable. In this paper we present a tool which performs this computation with low CPU time. Some other tools allowing to verify the self-checking properties of embedded blocks (like the strongly fault secure property of embedded PLAs and the self-testing property of embedded checkers), have also been developed and experimented.

Strongly Fault-Secure (SFS) circuits are known to achieve the TSC goal of producing a non-codeword as the first erroneous output due to a fault. Strongly Code-Disjoint (SCD) circuits always map non-codeword inputs to non-codeword outputs even in the presence of faults so long as the faults are undetectable. This paper presents a new generalized design method for the SFS and SCD realization of combinational circuits. The proposed design is simple, and always gives an SFS and SCD combinational circuit which implements any given logic function. The resulting SFS/SCD circuits can be connected in cascade with each other to construct a larger SFS/SCD circuit if each interface is fully exercised.

A new circuit and a transformer structure is described for a high-input-voltage converter operating at a high switching frequency. The two-MOSFET forward converter is suitable for a high-input-voltage converter. To increase the switching frequency, the reset period of the transformer core flux must be reduced. There are a few methods for decreasing the reset period. Increasing the transformer flyback voltage and reducing its stray capacitance are effective in decreasing the reset period without increasing power loss. A new two-MOSFET forward converter is proposed which uset the increased flyback voltage and a transformer structure to reduce the stray capacitance. The new converter using this transformer provides the basis for a 48-V, 100-W output, 270-V input converter operating at 200kHz with high efficiency (above 95%).

There have been few studies on formal approaches to the specification and realization of asynchronous sequential circuits. For synchronous sequential circuits, an algebraic method is proposed as one of such approaches, but it cannot be applied to asynchronous ones directly. This paper describes an algebraic method of specifying the abstract behavior of asynchronous sequential circuits. We select an daisy chain arbiter as an example of them. In the arbiter, state transitions are caused by input changes, and all the modules do not always make state transitions simultaneously. These are main obstacles to specify it in the same way as sychronous sequential circuits. In order to remove them, we modify the meaning of input in specifications and introduce pseudo state transitions so that we can regard all the modules as if they make state transitions simultaneously. This method can be applied to most of the other asynchronous sequential circuits.

This paper describes configuration and operation of a high-frequency link resonant inverter using cycloconverter techniques. In this inverter, a resonant link high-frequency voltage generated in a primary resonant inverter is isolated by a high-frequency transformer, then directly converted into a resonant link low-frequency voltage in a cycloconverter. The switching losses and surge voltage levels can be reduced by making all switches in the primary inverter and the cycloconverter operate at zero voltage. The relationship between characteristic impedance of the resonant circuit and the conversion efficiency, and the distortion factor characteristics of the output voltage waveforms are discussed by comparing of analytical and experimental results.

This paper presents an efficient heuristic algorithm for min-cut bisection of weighted hypergraphs. The proposed algorithm is based on a heuristic algorithm proposed by Kahng, which was devised for non-weighted hypergraph bisection, adopting a non-weighted graph called intersection graph to represent a given hypergraph. In the proposed algorithm, instead of an intersection graph, a bipartite graph called netgraph is newly introduced to explicitly represent the weights of nodes of a hypergraph. Using the netgraph, it is easy to partition a weighted hypergraph into two hypergraphs with same size. Computation time of the proposed method is O(m2), where m is the number of nodes of a given hypergraph. Experimental results with real circuit data show that the proposed method produces better solutions in shorter computation time compared with existing methods.

High frequency and low power 128/129 dual modulus prescaler ICs are developed for mobile communication applications, using 0.5 µm GaAs MESFET technology. Provided with an on-chip voltage regulator, a prescaler IC with an input amplifier operates in a wide frequency range from 200 MHz to 1,500 MHz at input power from -15 dBm to +17 dBm at the temperature of -30 to +120 with supply voltage of 2.7 V, 3.0 V and 5.0 V. At the same time, it demonstrated its low power characteristics consuming 3.68 mA with 3.0 V at +30 in operation, 0.16 mA while powered-off. Another prescaler IC without an input amplifier operates up to 1,650 MHz with Vdd=2.7 V, 3.0 V and 5.0 V at +30, dissipating 2.74 mA/3.0 V.

In this paper we propose a new timing verification technique named coded time-symbolic simulation, CTSS. Our interest is on simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values. Conventional logic simulation based on min/max delay model leads to over-pessimistic results. In our new method, the cases of possible delay values of each gate are encoded by binary vectors. The circuit behavior for all the possible combinations of the delay values are simulated based on symbolic simulation by assigning Boolean variables to the binary vectors. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. We implemented an efficient simulator by using shared binary decision diagrams (SBDD's) as internal representation of Boolean functions. We also propose novel techniques of analyzing the results of CTSS.

A hybrid integrated optical module composed of a silica-based planar lightwave circuit (PLC), a laser diode with an integrated monitor-photodiode, and a pin-photodiode is fabricated for use in high-performance, compact and cost-effective fiber optic subscriber systems. Its applicability to a wavelength-division-multiplex (WDM) system with a 1.3-µm bi-directional signal and a 1.5-µm one-way signal is demonstrated. The PLC was fabricated by a combination of flame hydrolysis deposition (FHD) and reactive ion etching (RIE), and it simultaneously achieved 1.3-µm/1.5-µm multi/demultiplexing and 1.3-µm Y-branching functions. The optical module exhibited insertion losses of 4.1dB at 1.31µm (including a Y-branch circuit loss of 3dB) and 0.5dB at 1.53µm. An optical output power of more than -4dBm was obtained from the optical module and the crosstalk was sufficiently low at less than -20dB between wavelengths of 1.3µm and 1.5µm. Temperature cycle tests on the optical module showed reliable and stable operation with an optical power fluctuation of less than 0.3dB for 500 cycles.

It is well known that the multiple-valued signed-digit (SD) arithmetic circuits have the attractive features of compactness and high-speed operation. However, both of these features have yet to be utilized fully. In this paper, we consider the application of a parallel-structure-based VLSI processor. A high-performance parallel-structure-based multiple-valued VLSI processor using the radix-2 SD number system is proposed. Its compactness makes the parallelism high under chip size limitations in comparison with the ordinary binary arithmetic circuits. Moreover, the speed of the single arithmetic module is very high in the SD arithmetic circuits, so that we can take advantage of the high-speed operation in the parallel-structure-based VLSI processor chip. The multiple-valued bidirectional current-mode technology is used not only in high-speed small sized arithmetic circuits, but also in reducing the number of connections in the parallel-structure-based VLSI processor. The proposed processor is specially developed for real-time digital control, where the performance is evaluated by delay time. Performance estimation using SPICE simulators shows that the delay time of proposed processor for matrix operations such as matrix multiplication is greatly reduced in comparison with a conventional binary processor.

The characteristics of an optical functional integrated circuit and its applications are discussed. This circuit is based upon a Mach-Zehnder interferometer type waveguide device employing thermo-optic effect. This circuit is compact, cost-effective and practical. One proposed application is an optical loopback circuit to test both OCU loop 1 and DSU loop C. This optical loopback circuit with an attenuator and space switches is formed on a common silicon substrate, and using this circuit both loopback and line tests are independently available at the same access point. The other is an optical selector. This optical selector with WDM-MUX/DMUX and space switches is formed on a common silicon substrate, and using this selector, wavelength selection from medium density WDM (MDWDM) signal can be performed. Each MDWDM signal carries both AM and FM-FDM video signals modulated by Subcarrier Multiplexing (SCM) techniques. This selector can be wired in point-to-multipoint configurations to home video appliances.