IEICE TRANSACTIONS on Fundamentals
Coded Time-Symbolic Simulation for Timing Verification of Logic Circuits
Summary :
In this paper we propose a new timing verification technique named coded time-symbolic simulation, CTSS. Our interest is on simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values. Conventional logic simulation based on min/max delay model leads to over-pessimistic results. In our new method, the cases of possible delay values of each gate are encoded by binary vectors. The circuit behavior for all the possible combinations of the delay values are simulated based on symbolic simulation by assigning Boolean variables to the binary vectors. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. We implemented an efficient simulator by using shared binary decision diagrams (SBDD's) as internal representation of Boolean functions. We also propose novel techniques of analyzing the results of CTSS.
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- IEICE TRANSACTIONS on Fundamentals Vol.E75-A No.10 pp.1247-1254
- Publication Date
- 1992/10/25
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- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Nagisa ISHIURA, Yutaka DEGUCHI, Shuzo YAJIMA, "Coded Time-Symbolic Simulation for Timing Verification of Logic Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E75-A, no. 10, pp. 1247-1254, October 1992, doi: .
Abstract: In this paper we propose a new timing verification technique named coded time-symbolic simulation, CTSS. Our interest is on simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values. Conventional logic simulation based on min/max delay model leads to over-pessimistic results. In our new method, the cases of possible delay values of each gate are encoded by binary vectors. The circuit behavior for all the possible combinations of the delay values are simulated based on symbolic simulation by assigning Boolean variables to the binary vectors. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. We implemented an efficient simulator by using shared binary decision diagrams (SBDD's) as internal representation of Boolean functions. We also propose novel techniques of analyzing the results of CTSS.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e75-a_10_1247/_p
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@ARTICLE{e75-a_10_1247,
author={Nagisa ISHIURA, Yutaka DEGUCHI, Shuzo YAJIMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Coded Time-Symbolic Simulation for Timing Verification of Logic Circuits},
year={1992},
volume={E75-A},
number={10},
pages={1247-1254},
abstract={In this paper we propose a new timing verification technique named coded time-symbolic simulation, CTSS. Our interest is on simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values. Conventional logic simulation based on min/max delay model leads to over-pessimistic results. In our new method, the cases of possible delay values of each gate are encoded by binary vectors. The circuit behavior for all the possible combinations of the delay values are simulated based on symbolic simulation by assigning Boolean variables to the binary vectors. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. We implemented an efficient simulator by using shared binary decision diagrams (SBDD's) as internal representation of Boolean functions. We also propose novel techniques of analyzing the results of CTSS.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - Coded Time-Symbolic Simulation for Timing Verification of Logic Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1247
EP - 1254
AU - Nagisa ISHIURA
AU - Yutaka DEGUCHI
AU - Shuzo YAJIMA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E75-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1992
AB - In this paper we propose a new timing verification technique named coded time-symbolic simulation, CTSS. Our interest is on simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values. Conventional logic simulation based on min/max delay model leads to over-pessimistic results. In our new method, the cases of possible delay values of each gate are encoded by binary vectors. The circuit behavior for all the possible combinations of the delay values are simulated based on symbolic simulation by assigning Boolean variables to the binary vectors. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. We implemented an efficient simulator by using shared binary decision diagrams (SBDD's) as internal representation of Boolean functions. We also propose novel techniques of analyzing the results of CTSS.
ER -
English
