A negation-limited circuit is a combinational circuit which includes at most [log(n1)] NOT gates. We show a relationship between the size of negation-limited circuits computing clique functions and the number of NOT gates in the circuits.

We exactly determine the number of negations needed to compute the parity functions and the complement of the parity functions. We show that with k NOT gates, parity can be computed on at most 2k+11 variables, and parity complement on at most 2k+12 variables. The two bounds are shown to be tight.

This paper presents a method, called reduced scan shift, which generates short test sequences for full scan circuits. In this method, scan shift operations can be reduced, i.e., not all but part of flip-flops (FFs) are controlled and observed. This method, unlike partial scan methods, does not decrease fault coverage. In the reduced scan shift, test vectors for the combinational part of a circuit are fistly generated. Since short test sequence will be obtained from the small test vectors set, test compaction techniques are used in the test vector generation. For each test vector in the obtained test set, it is found which FFs should be controlled or observed. And then a scan chain is configured so that FFs more frequently required to be controlled (observed) can be located close to the scan input (output). After the scan chain is configured, the scan shift requirement is examined for the essential faults of each test vector. Essential fault is defined to be a fault which is detected by only one test vector but not other test vectors. The order of test vectors is carefully determined by comparing the scan control requirement of a test vector with the scan observation requirement of another test vector so that unnecessary scan shift operations only for controlling or observing FFs can be reduced. A method of determining the order of test vectors with state transition is additionally described. The effectiveness of the proposed method is shown by the experimental results for benchmark circuits.

In this letter a new method for controlling chaos is proposed. Although different several methods based on the OGY- and the OPF-method perturb a value of an accessible system parameter, the proposed method perturbs the only timing of switching three values of a parameter. We apply the proposed method to the well-known Chua's circuit on computer simulations. The chaotic orbits in the Rössler type- and the double scroll type-attractor can be stabilized on several unstable periodic orbits embedded within these attractors.

In this letter an SR-latch circuit using Hopfield neural networks is introduced. An energy function suited for a neural SR-latch circuit is defined for which the global convergence is guaranteed. We also demonstrate how to compose master-slave (M/S) SR- and JK-flip flops of novel SR-latch circuits, and further an asynchronous binary counter of M/S JK-flip flops. Computer simulations are included to illustrate how each presented circuit operates.

This paper presents an analysis of the control characteristics of the series resonant converter with a parallel resonant circuit, especially under parallel resonant frequency. Operations of the circuit are classified into several modes. The control characteristics are calculated using the equations derived from equivalent circuits, and are verified by the experiments. From the analysis, the mechanism of a jumping phenomenon in the closed-loop control characteristics is clarified.

A 3.2 GHz, 50 mW, 1 V, GaAs clock pulse generator (CG) based on a phase-locked loop (PLL) circuit has been designed for use as an on-chip clock generator in future high speed processor LSIs. 0.5 µm GaAs MESFET and DCFL circuit technologies have been used for the CG, which consists of 224 MESFETs. An "enhanced charge-up current" inverter has been specially designed for a low power and high speed voltage controlled oscillator (VCO). In this new inverter, a voltage controlled dMESFET is combined in parallel with the load dMESFET of a conventional DCFL inverter. This voltage controlled dMESFET produces an additional charge-up current resulting in the new VCO obtaining a much higher oscillation frequency than that of a ring oscillator produced with a conventional inverter. With a single 1 V power supply (Vdd), SPICE calculation results showed that the VCO tuning range was 2.25 GHz to 3.65 GHz and that the average VCO gain was approximately 1.4 GHz/V in the range of a control voltage (Vc) from 0 to 1 V. Simulation also indicated that at a Vdd of 1 V the CG locked on a 50 MHz external clock and generated a 3.2 GHz internal clock (=50 MHz64). The jitter and power dissipation of the CG at 3.2 GHz oscillation and a Vdd of 1 V were less than 8.75 psec and 50 mW, respectively. The typical lock range was 2.90 GHz to 3.59 GHz which corresponded to a pull-in range of 45.3 MHz to 56.2 MHz.

A programmable clock generator, based on a phase-locked loop (PLL) circuit, has been developed with 0.5 µm CMOS triple-layer Al interconnection technology for use as an on-chip clock generator in a 300-MHz video signal processor. The PLL-based clock generator generates a clock signal whose frequency ranges from 50 to 350 MHz which is an integral multiple, from 2 to 16, of an external clock frequency. In order to achieve stable operation within this wide range, a voltage controlled oscillator (VCO) with selectable low VCO gain characteristics has been developed. Experimental results show that the clock generator generates a 297-MHz clock with a 27-MHz external clock, with jitter of 180 ps and power dissipation of 120 mW at 3.3-V power supply, and it can also oscillate up to 348 MHz with a 31.7-MHz external clock.

An emitter–coupled pair with a dynamic bias current and a source–coupled pair with a dynamic bias current are proposed as an exponential–law element and a square–law element that operate as a floating bipolar junction transistor (BJT) and a floating MOS field–effect transistor (MOSFET). In bipolar technology, a hyperbolic sine function circuit and a hyperbolic cosine function circuit are easily obtained by subtracting and summing the output currents of two symmetrical exponential–law elements with positive and negative input signals. In the same manner, an operational transconductance amplifier (OTA) and a squaring circuit are obtained by subtracting and summing the output currents of two symmetrical square-law elements with positive and negative input signals in CMOS technology. The proposed OTA and squaring circuit possess the widest input voltage range ever reported.

More than 200 papers, two special issues (Journal of Circuits, Systems, and Computers, March, June, 1993, and IEEE Trans. on Circuits and Systems, vol.40, no.10, October 1993), an International workshop on "Chua's Circuit: chaotic phenomena and applications" at NOLTA'93, and a book (Edited by R. N. Madan, World Scientific, 1993) on Chua's circuit have been published since its inception a decade ago. This review paper attempts to present an overview of these timely publications, almost all within the last 6 months, and to identify four milestones of this very active research area. An important milestone is the recent fabrication of a monolithic Chua's circuit. The robustness of this IC chip demonstrates that an array of Chua's circuits can also be fabricated into a monolithic chip, thereby opening the floodgate to many unconventional applications in information technology, synergetics, and even music. The second milestone is the recent global unfolding of Chua's circuit, obtained by adding a linear resistor in series with the inductor to obtain a canonical Chua's circuit--now generally referred to as Chua's oscillator. This circuit is most significant because it is structurally the simplest (it contain only 6 circuit elements) but dynamically the most complex among all nonlinear circuits and systems described by a 21–parameter family of continuous odd–symmetric piecewise–linear vector fields. The third milestone is the recent discovery of several important new phenomena in Chua's Circuits, e.g., stochastic resonance, chaos–chaos type intermittency, 1/f noise spectrum, etc. These new phenomena could have far-reaching theoretical and practical significance. The fourth milestone is the theoretical and experimental demonstration that Chua's circuit can be easily controlled from a chaotic regime to a prescribed periodic or constant orbit, or it can be synchronized with 2 or more identical Chua's circuits, operating in an oscillatory, or a chaotic regime. These recent breakthroughs have ushered in a new era where chaos is deliberately created and exploited for unconventional applications, e.g., secure communication.

A MOS VCO which has improved linearity of oscillation frequency versus control voltage and has no 1/2 divider is studied. The improved VCO characteristic has been obtained by the use of only two additional transistors, one of which has a role of a load and another of which has a role of a control current source in a differential type delay cell.

Transistor stuck–open faults in CMOS devices are such that they force combinational circuits to exhibit sequential behaviors. It has been proved that, in general, stuck–open faults can not be modeled as stuck–at faults and, therefore, a sequence of two consecutive test vectors is necessary to guarantee stuck–open fault detection. In this paper we propose a technique to modify CMOS circuits in such a way that any stuck–open fault in the circuit can be detected using only a single test pattern. The amount of additional logic required to achieve the goal is rather limited: Two pass transistors, one input line, and one inverter (or buffer) at the output of the circuit are sufficient to make stuck–open faults detectable by test patterns generated by usual stuck–at fault test generators.

A novel optoelectronic mesoscopic neural device is proposed. This device operates in a neural manner, involving the electron interference and the laser threshold characteristics. The optical output is a 2–dimensional image, and can also be colored, if the light emitting elements are fabricated to form the picture elements in 3–colors, i.e. R, G, and B. The electron waveguiding in the proposed device is analyzed, on the basis of the analogy between the Schrödinger's equation and the Maxwell's wave equation. The nonlinear neural connection is achieved, as a result of the superposition an the interferences among electron waves transported through different waveguides. The sizes of the critical elements of this device are estimated to be within the reach of the present day technology. This device exceeds the conventional VLSI neurochips by many orders of magnitude, in the number of neurons per unit area, as well as in the speed of operation.

Gate-controlled negative differential resistance (NDR) due to interband tunneling has been observed at room temperature in a Surface Tunnel Transistor (STT). The STT consists of a highly degenerate p+-drain, an n+-doped channel with an insulated gate, and an n+-source connected to the channel. To demonstrate application as a functional device, a bistable circuit consisting of only one STT and one load resistor was organized and its operation was confirmed. The obtained valley current in the NDR characteristics of the STT, however, is relatively large and limits the device performance. In order to clarify the origin of the valley current, we fabricated p+-n+ tunnel diodes in which growth interruption was done at the pn junction, and investigated the dependence of the NDR characteristics on both the impurity concentration at the regrown interface and the temperature. These measurements indicate that the valley current is mainly caused by the excess tunneling current through traps formed by the residual oxygen at the regrown interface.

Recent achievements in low-voltage and low-power circuit techniques are reported in this paper. DC current in low-voltage CMOS circuits stemming from the subthreshold current in MOS transistors, is effectively reduced by applying switched-power-line schemes. The AC current charging the capacitance in DRAM memory arrays is reduced by a partial activation of array blocks during the active mode and by a charge recycle during the refresh mode. A very-low-power reference-voltage generator is also reported to control the internal chip voltage precisely. These techniques will open the way to using giga-scale LSIs in battery-operated portable equipment.

This paper describes CMOS embedded RAMs we developed utilizing 1.3 µm and 0.8 µm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 µm process technology and developed a 4 kW9 b single-port embedded RAM with 5 ns access time and 100 mW power dissipation during32 MHz operation, and a 1 kW9 b dual-port embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.

It is demonstrated that the enhancement in the functional capability of an elemental transistor is quite essential in developing human-like intelligent electronic systems. For this purpose we have introduced the concept of four-terminal devices. Four-terminal devices have an additional dimension in the degree of freedom in controlling currents as compared to the three-terminal devices like bipolar and MOS transistors. The importance of the four-terminal device concept is demonstrated taking the neuron MOS transistor (abbreviated as neuMOS or νMOS) and its circuit applications as examples. We have found that any Boolean functin can be realized by a two-stage configuratin of νMOS inverters. In addition, the variable threshold nature of the device allows us to build real-time reconfigurable logic circuits (no floating gate charging effect is involved in varying the threshold). Based on the principle, we have developed Soft-Hardware Logic Circuits and Real-Time Rule-Variable Data Matching Circuits. A winner-take-all circuit which finds the largest signal by hardware parallel processing has been also developed. The circuit is applied to building an associative memory which is different from Hopfield network in both principle and operation. The hardware algorithm in which binary, multivalue, and analog operations are merged at a very device level is quite essential to establish intelligent information processing systems based on highly flexible, real-time programmable hardwares realized by four-terminal devices.

This paper presents a low-power 8-valued cellular array VLSI for high-speed image processing based on logical neighborhood operations with 33 windows. This array is useful for performing low-level image processing such as noise removal and edge detection, in intelligent integrated systems where immediate response to input change as well as high throughput is needed. In order to achieve high-speed image processing, template matching for neighborhood operations can be performed in parallel on each row. Each row of the image is operated in a pipelining manner. The direct 8-valued encoding of the matched results for three different 33 masks makes it possible to reduce the number of operations by one-third. In the hardware implementation, the matching cell for logical neighborhood operations can be implemented compactly using MOS transistors with different threshold voltage, which are programmed by multiple ion implants. Moreover, a new literal circuit for detecting multiple-valued signals using a dynamic design style eliminates hazards due to timing skews in the difference of various input voltage levels, so that the dynamic power dissipation of the proposed circuit is greatly reduced. Finally, it is demonstrated that the processing time of the proposed cellular array is reduced to about 40 percent in comparison with that of a corresponding binary circuit when power dissipation/area = 0.3 W/100 mm2.

An analog circuit is devised which selects and outputs the kth largest element among n input voltages. The circuit is composed of n basic transconductance amplifiers connected mutually with an O(n) length wire, thus the complexity of the circuit is O(n). The circuit becomes particularly simple for the case of the selection of the median of inputs.

It is of significantly importance in relation to the problem of diagnosis of deviation faults in linear analog circuits to check whether or not it is possible to uniquely determine the element-values in a given linear analog circuit from the node-voltage measurements at its accessible nodes and then of giving a method for actual computation of the element-values if it is possible, under the assumption that i) the circuit is of known topology (and of known element-kinds if possible) and ii) the actual value of each element-value of the circuit almost always deviates from the design value and is not known exactly. In this paper, the problem of checking the unique determinability of the element-values is called the element-value determinability problem, and its solutions which have been obtained until now are reviewed in perspectives to designing a publicly available user-oriented analog circuit diagnosis system.