Stuck–Open Fault Detection in CMOS Circuits Using Single Test Patterns
Summary :
Transistor stuck–open faults in CMOS devices are such that they force combinational circuits to exhibit sequential behaviors. It has been proved that, in general, stuck–open faults can not be modeled as stuck–at faults and, therefore, a sequence of two consecutive test vectors is necessary to guarantee stuck–open fault detection. In this paper we propose a technique to modify CMOS circuits in such a way that any stuck–open fault in the circuit can be detected using only a single test pattern. The amount of additional logic required to achieve the goal is rather limited: Two pass transistors, one input line, and one inverter (or buffer) at the output of the circuit are sufficient to make stuck–open faults detectable by test patterns generated by usual stuck–at fault test generators.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E77-A No.11 pp.1977-1979
- Publication Date
- 1994/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Computer Aided Design (CAD)
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Enrico MACII, Qing XU, "Stuck–Open Fault Detection in CMOS Circuits Using Single Test Patterns" in IEICE TRANSACTIONS on Fundamentals,
vol. E77-A, no. 11, pp. 1977-1979, November 1994, doi: .
Abstract: Transistor stuck–open faults in CMOS devices are such that they force combinational circuits to exhibit sequential behaviors. It has been proved that, in general, stuck–open faults can not be modeled as stuck–at faults and, therefore, a sequence of two consecutive test vectors is necessary to guarantee stuck–open fault detection. In this paper we propose a technique to modify CMOS circuits in such a way that any stuck–open fault in the circuit can be detected using only a single test pattern. The amount of additional logic required to achieve the goal is rather limited: Two pass transistors, one input line, and one inverter (or buffer) at the output of the circuit are sufficient to make stuck–open faults detectable by test patterns generated by usual stuck–at fault test generators.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e77-a_11_1977/_p
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@ARTICLE{e77-a_11_1977,
author={Enrico MACII, Qing XU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Stuck–Open Fault Detection in CMOS Circuits Using Single Test Patterns},
year={1994},
volume={E77-A},
number={11},
pages={1977-1979},
abstract={Transistor stuck–open faults in CMOS devices are such that they force combinational circuits to exhibit sequential behaviors. It has been proved that, in general, stuck–open faults can not be modeled as stuck–at faults and, therefore, a sequence of two consecutive test vectors is necessary to guarantee stuck–open fault detection. In this paper we propose a technique to modify CMOS circuits in such a way that any stuck–open fault in the circuit can be detected using only a single test pattern. The amount of additional logic required to achieve the goal is rather limited: Two pass transistors, one input line, and one inverter (or buffer) at the output of the circuit are sufficient to make stuck–open faults detectable by test patterns generated by usual stuck–at fault test generators.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Stuck–Open Fault Detection in CMOS Circuits Using Single Test Patterns
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1977
EP - 1979
AU - Enrico MACII
AU - Qing XU
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E77-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1994
AB - Transistor stuck–open faults in CMOS devices are such that they force combinational circuits to exhibit sequential behaviors. It has been proved that, in general, stuck–open faults can not be modeled as stuck–at faults and, therefore, a sequence of two consecutive test vectors is necessary to guarantee stuck–open fault detection. In this paper we propose a technique to modify CMOS circuits in such a way that any stuck–open fault in the circuit can be detected using only a single test pattern. The amount of additional logic required to achieve the goal is rather limited: Two pass transistors, one input line, and one inverter (or buffer) at the output of the circuit are sufficient to make stuck–open faults detectable by test patterns generated by usual stuck–at fault test generators.
ER -
English
