This paper describes CMOS embedded RAMs we developed utilizing 1.3 µm and 0.8 µm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 µm process technology and developed a 4 kW9 b single-port embedded RAM with 5 ns access time and 100 mW power dissipation during32 MHz operation, and a 1 kW9 b dual-port embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.

This paper describes a 0.8-µm CMOS LSI developed for a 156-Mb/s serial interface in ATM switching systems. Recently, there have been increasing problems of connector pin neck and higher power consumption when enhancing switching system capacity. To overcome these problems, we have developed an LSI with a high-speed interface by using CMOS technology to achieve low power consumption. A low-swing differential signal level is used to achieve 156-Mb/s data transmission. We named this new circuit technique ALTS (Advanced Low-level Transmission circuit System). Using the LSI, transmission can be achieved between boards or racks through a 10-meter twisted pair cable. The LSI has a 156-Mb/s transmitter-receiver, a serial-to-parallel converter and a parallel-to-serial converter. It performs 19.5-Mb/s parallel data/156-Mb/s serial data conversion and 156-Mb/s serial data transmission. In addition, it has a bit phase synchronizer and cell synchronizer, which enables it to transmit and synchronize serial data without a paralleled clock or a paralleled cell top signal, by distributing a common 156-MHz clock and a common cell top signal to the whole system. We evaluated the bit error rate and timing margin on data transmission under several conditions. The results show that we can apply this LSI to commercially available ATM switching systems. This paper also describes methods of expanding switch capacity and transmitting 624-Mb/s data using this LSI.

This paper describes circuit techniques of a 5 ns, 4 kw9 b embedded RAM for standard cell ASICs applying 0.8 µm pure CMOS triple metal technology. The design goals of the above techniques were high speed, low power consumption, and access time stability even when the RAM configuration is changed in word and bit numbers. A one-chip 4,096-channel time switch VLSI for digital switching systems is also described as an example of application of these RAMs to standard cell CMOS ASICs. This chip has 600 mW power consumption during 32 MHz operation.