CMOS Embedded RAMs for Digital Communication Systems

Masao MIZUKAMI; Yoichi SATOH; Takahiko KOZAKI; Yasuo MIKAMI

CMOS Embedded RAMs for Digital Communication Systems

Masao MIZUKAMI, Yoichi SATOH, Takahiko KOZAKI, Yasuo MIKAMI

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This paper describes CMOS embedded RAMs we developed utilizing 1.3 µm and 0.8 µm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 µm process technology and developed a 4 kW9 b single-port embedded RAM with 5 ns access time and 100 mW power dissipation during32 MHz operation, and a 1 kW9 b dual-port embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.8 pp.1361-1368

Publication Date: 1994/08/25

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Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)

Category: General Technology

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Masao MIZUKAMI, Yoichi SATOH, Takahiko KOZAKI, Yasuo MIKAMI, "CMOS Embedded RAMs for Digital Communication Systems" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 8, pp. 1361-1368, August 1994, doi: .
Abstract: This paper describes CMOS embedded RAMs we developed utilizing 1.3 µm and 0.8 µm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 µm process technology and developed a 4 kW9 b single-port embedded RAM with 5 ns access time and 100 mW power dissipation during32 MHz operation, and a 1 kW9 b dual-port embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_8_1361/_p

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@ARTICLE{e77-c_8_1361,
author={Masao MIZUKAMI, Yoichi SATOH, Takahiko KOZAKI, Yasuo MIKAMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={CMOS Embedded RAMs for Digital Communication Systems},
year={1994},
volume={E77-C},
number={8},
pages={1361-1368},
abstract={This paper describes CMOS embedded RAMs we developed utilizing 1.3 µm and 0.8 µm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 µm process technology and developed a 4 kW9 b single-port embedded RAM with 5 ns access time and 100 mW power dissipation during32 MHz operation, and a 1 kW9 b dual-port embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - CMOS Embedded RAMs for Digital Communication Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 1361
EP - 1368
AU - Masao MIZUKAMI
AU - Yoichi SATOH
AU - Takahiko KOZAKI
AU - Yasuo MIKAMI
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1994
AB - This paper describes CMOS embedded RAMs we developed utilizing 1.3 µm and 0.8 µm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 µm process technology and developed a 4 kW9 b single-port embedded RAM with 5 ns access time and 100 mW power dissipation during32 MHz operation, and a 1 kW9 b dual-port embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.
ER -