This paper describes CMOS embedded RAMs we developed utilizing 1.3 µm and 0.8 µm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 µm process technology and developed a 4 kW9 b single-port embedded RAM with 5 ns access time and 100 mW power dissipation during32 MHz operation, and a 1 kW9 b dual-port embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.

A modified illumination technique recently developed is known to improve the resolution and DOF (depth of focus) dramatically. But, it requires substantial modification in optical projection system and has some problems such as low throughput caused by low intensity and poor uniformity. And it is very difficult to adjust illumination source according to pattern changes. To solve these problems, we developed a new illumination technique, named ATOM (Advanced Tilted illumination On Mask) which applies the same concept as quadrupole illumination technique but gives many advantages over conventional techniques. This newly inserted mask gives drastic improvements in many areas such as DOF, resolution, low illumination intensity loss, and uniformity. In our experiments, we obtained best resolution of 0.28µm and 2.0µm DOF for 0.36µm feature sizes with i-line stepper, which is two times as wide as that of conventional illumination technique. We also obtained 0.22µm resolution and 2.0µm DOF for 0.28µm with 0.45NA KrF excimer laser stepper. For complex device patterns, more than 1.5 times wider DOF could be obtained compared to conventional illumination technique. From these results, we can conclude that 2nd generation of 64M DRAM with 0.3µm design rule can be printed with this technology combined with high NA (0.5) i-line steppers. With KrF excimer laser stepper, 256M DRAM can be printed with wide DOF.

Characterization of silicon devices incorporating the capacitor which uses ferroelectric thin films as capacitor dielectrics is presented. As cases in point, a DRAM cell capacitor and an analog/digital silicon IC using the thin film of barium strontium titanate (Ba1-xSRxTiO3) are examined. Production and characterization of the ferroelectric thin films are also described, focusing on a Metal Organic Deposition technique and liquid source CVD.

Four circuit techniques and a layout design scheme were proposed to realize a 2 Mb VRAM used 0.8 µm technology. They are the enhanced circuit technologies for high speed operation, the functional circuit design and the effective repair schemes for a VRAM, the low power consumption techniques to active and standby mode and a careful layout design scheme realizing high noise immunity. Using these design techniques, a 2 Mb VRAM is suitable for the graphics application of a 5125128 pixels basis screen, with a clear mode of 4.6 GByte/sec and a 4-multi column write mode of 400 MByte/sec, even using the same 0.8 µm technology as the previous VRAM (1 Mb) was realized.

This paper describes the architecture and simulated performance of a proposed Integrated Memory Array Processor (IMAP). The IMAP is an LSI which integrates a large capacity memory and a one dimensional SIMD processor array on a single chip. The IMAP holds, in its on-chip memory, data which at the same time can be processed using a one dimensional SIMD processor integrated on the same chip. All processors can access their individual parts of memory columns at the same time. Thus, it has very high processor-memory data transfer bandwidth, and has no memory access bottleneck. Data stored in the memory can be accessed from outside of the IMAP via a conventional memory interface same as a VRAM. Since the SIMD processors on the IMAP are configured in a one dimensional array, multiple IMAPs could easily be connected in series to create a larger processor and memory configuration. To estimate the performance of such an IMAP, a system architecture and instruction set were first defined, and on the basis of those two, a simulator and an assembly language were then developed. In this paper, simulation results are presented which indicate the performance of an IMAP in both image processing and artificial neural network calculations.