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Kohji MITANI Hiroshi SHIMAMOTO Yoshihiro FUJITA
We have developed an experimental 4 K 2 K pixel progressive scan color camera system. This new camera system has a data rate of 297 MHz pixel/sec and 60 frame/sec and we are sure that horizontal and vertical limiting resolution of 1500 TVL (TV lines) can be achieved on a color monitor. Instead of the previous approach of improving resolution simply by increasing the pixel count in a imager, a novel four-sensor pickup method with 2/3 inch 2 million pixel CMD (Charge Modulation Device) imagers is used in this system. These sensors have 1920 (H) 1035 (V) pixels within a 16:9 wide aspect image area and are successfully driven at 148 M pixel/sec in the progressive scan mode. In the four-sensor pickup method, two sensors are used for green and the rest are for red and blue. A spatial offset imaging method in the diagonal direction was applied to the two green sensors to improve the horizontal and vertical resolution effectively. The horizontal and vertical resolution of the red and blue signals become half that of the green signal, because only one 2 M-pixel imager is used for each signal. The resolution of this system, however, is not degraded so much because the luminance signal is mainly composed of green signals.
Miki SATO Akihiko SUGIYAMA Osamu HOSHUYAMA Nobuyuki YAMASHITA Yoshihiro FUJITA
This paper proposes near-field sound-source localization based on crosscorrelation of a signed binary code. The signed binary code eliminates multibit signal processing for simpler implementation. Explicit formulae with near-field assumption are derived for a two microphone scenario and extended to a three microphone case with front-rear discrimination. Adaptive threshold for enabling and disabling source localization is developed for robustness in noisy environment. The proposed sound-source localization algorithm is implemented on a fixed-point DSP. Evaluation results in a robot scenario demonstrate that near-field assumption and front-rear discrimination provides almost 40% improvement in DOA estimation. A correct detection rate of 85% is obtained by a robot in a home environment.
Yoshihiro FUJITA Nobuyuki YAMASHITA Shin'ichiro OKAZAKI
This paper describes the architecture and simulated performance of a proposed Integrated Memory Array Processor (IMAP). The IMAP is an LSI which integrates a large capacity memory and a one dimensional SIMD processor array on a single chip. The IMAP holds, in its on-chip memory, data which at the same time can be processed using a one dimensional SIMD processor integrated on the same chip. All processors can access their individual parts of memory columns at the same time. Thus, it has very high processor-memory data transfer bandwidth, and has no memory access bottleneck. Data stored in the memory can be accessed from outside of the IMAP via a conventional memory interface same as a VRAM. Since the SIMD processors on the IMAP are configured in a one dimensional array, multiple IMAPs could easily be connected in series to create a larger processor and memory configuration. To estimate the performance of such an IMAP, a system architecture and instruction set were first defined, and on the basis of those two, a simulator and an assembly language were then developed. In this paper, simulation results are presented which indicate the performance of an IMAP in both image processing and artificial neural network calculations.
Yoshiharu AIMOTO Tohru KIMURA Yoshikazu YABE Hideki HEIUCHI Youetsu NAKAZAWA Masato MOTOMURA Takuya KOGA Yoshihiro FUJITA Masayuki HAMADA Takaho TANIGAWA Hajime NOBUSAWA Kuniaki KOYAMA
We have developed a parallel image processing RAM (PIP-RAM) which integrates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0. 38-µm CMOS 64-Mb DRAM process technology. It achieves 7. 68-GIPS processing performance and 3. 84-GB/s memory bandwidth with only 1-W power dissipation (@ 30-MHz), and the key to this performance is the DRAM design. This paper presents the key circuit techniques employed in the DRAM design: 1) a paged-segmentation accessing scheme that reduces sense amplifier power dissipation, and 2) a clocked low-voltage-swing differential-charge-transfer scheme that reduces data line power dissipation with the help of a multi-phase synchronization DRAM control scheme. These techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.