Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM

Yoshiharu AIMOTO; Tohru KIMURA; Yoshikazu YABE; Hideki HEIUCHI; Youetsu NAKAZAWA; Masato MOTOMURA; Takuya KOGA; Yoshihiro FUJITA; Masayuki HAMADA; Takaho TANIGAWA; Hajime NOBUSAWA; Kuniaki KOYAMA

Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM

Yoshiharu AIMOTO, Tohru KIMURA, Yoshikazu YABE, Hideki HEIUCHI, Youetsu NAKAZAWA, Masato MOTOMURA, Takuya KOGA, Yoshihiro FUJITA, Masayuki HAMADA, Takaho TANIGAWA, Hajime NOBUSAWA, Kuniaki KOYAMA

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We have developed a parallel image processing RAM (PIP-RAM) which integrates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0. 38-µm CMOS 64-Mb DRAM process technology. It achieves 7. 68-GIPS processing performance and 3. 84-GB/s memory bandwidth with only 1-W power dissipation (@ 30-MHz), and the key to this performance is the DRAM design. This paper presents the key circuit techniques employed in the DRAM design: 1) a paged-segmentation accessing scheme that reduces sense amplifier power dissipation, and 2) a clocked low-voltage-swing differential-charge-transfer scheme that reduces data line power dissipation with the help of a multi-phase synchronization DRAM control scheme. These techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.

Publication: IEICE TRANSACTIONS on Electronics Vol.E81-C No.5 pp.759-767

Publication Date: 1998/05/25

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Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)

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Yoshiharu AIMOTO, Tohru KIMURA, Yoshikazu YABE, Hideki HEIUCHI, Youetsu NAKAZAWA, Masato MOTOMURA, Takuya KOGA, Yoshihiro FUJITA, Masayuki HAMADA, Takaho TANIGAWA, Hajime NOBUSAWA, Kuniaki KOYAMA, "Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM" in IEICE TRANSACTIONS on Electronics, vol. E81-C, no. 5, pp. 759-767, May 1998, doi: .
Abstract: We have developed a parallel image processing RAM (PIP-RAM) which integrates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0. 38-µm CMOS 64-Mb DRAM process technology. It achieves 7. 68-GIPS processing performance and 3. 84-GB/s memory bandwidth with only 1-W power dissipation (@ 30-MHz), and the key to this performance is the DRAM design. This paper presents the key circuit techniques employed in the DRAM design: 1) a paged-segmentation accessing scheme that reduces sense amplifier power dissipation, and 2) a clocked low-voltage-swing differential-charge-transfer scheme that reduces data line power dissipation with the help of a multi-phase synchronization DRAM control scheme. These techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e81-c_5_759/_p

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@ARTICLE{e81-c_5_759,
author={Yoshiharu AIMOTO, Tohru KIMURA, Yoshikazu YABE, Hideki HEIUCHI, Youetsu NAKAZAWA, Masato MOTOMURA, Takuya KOGA, Yoshihiro FUJITA, Masayuki HAMADA, Takaho TANIGAWA, Hajime NOBUSAWA, Kuniaki KOYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM},
year={1998},
volume={E81-C},
number={5},
pages={759-767},
abstract={We have developed a parallel image processing RAM (PIP-RAM) which integrates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0. 38-µm CMOS 64-Mb DRAM process technology. It achieves 7. 68-GIPS processing performance and 3. 84-GB/s memory bandwidth with only 1-W power dissipation (@ 30-MHz), and the key to this performance is the DRAM design. This paper presents the key circuit techniques employed in the DRAM design: 1) a paged-segmentation accessing scheme that reduces sense amplifier power dissipation, and 2) a clocked low-voltage-swing differential-charge-transfer scheme that reduces data line power dissipation with the help of a multi-phase synchronization DRAM control scheme. These techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM
T2 - IEICE TRANSACTIONS on Electronics
SP - 759
EP - 767
AU - Yoshiharu AIMOTO
AU - Tohru KIMURA
AU - Yoshikazu YABE
AU - Hideki HEIUCHI
AU - Youetsu NAKAZAWA
AU - Masato MOTOMURA
AU - Takuya KOGA
AU - Yoshihiro FUJITA
AU - Masayuki HAMADA
AU - Takaho TANIGAWA
AU - Hajime NOBUSAWA
AU - Kuniaki KOYAMA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1998
AB - We have developed a parallel image processing RAM (PIP-RAM) which integrates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0. 38-µm CMOS 64-Mb DRAM process technology. It achieves 7. 68-GIPS processing performance and 3. 84-GB/s memory bandwidth with only 1-W power dissipation (@ 30-MHz), and the key to this performance is the DRAM design. This paper presents the key circuit techniques employed in the DRAM design: 1) a paged-segmentation accessing scheme that reduces sense amplifier power dissipation, and 2) a clocked low-voltage-swing differential-charge-transfer scheme that reduces data line power dissipation with the help of a multi-phase synchronization DRAM control scheme. These techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.
ER -