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Yoshiharu AIMOTO Tohru KIMURA Yoshikazu YABE Hideki HEIUCHI Youetsu NAKAZAWA Masato MOTOMURA Takuya KOGA Yoshihiro FUJITA Masayuki HAMADA Takaho TANIGAWA Hajime NOBUSAWA Kuniaki KOYAMA
We have developed a parallel image processing RAM (PIP-RAM) which integrates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0. 38-µm CMOS 64-Mb DRAM process technology. It achieves 7. 68-GIPS processing performance and 3. 84-GB/s memory bandwidth with only 1-W power dissipation (@ 30-MHz), and the key to this performance is the DRAM design. This paper presents the key circuit techniques employed in the DRAM design: 1) a paged-segmentation accessing scheme that reduces sense amplifier power dissipation, and 2) a clocked low-voltage-swing differential-charge-transfer scheme that reduces data line power dissipation with the help of a multi-phase synchronization DRAM control scheme. These techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.
Takaho TANIGAWA Akira YOSHINO Hiroki KOGA Shuichi OHYA
Stacked capacitor dynamic random access memory(DRAM) cells with both NMOS and PMOS cell transistors(Lg=0.4µm) were fabricated on ultra-thin SIMOX(separation by implantation of oxygen) substrates, and the data retention time was compared with that of a bulk counterpart. A DATA retention time of 550 sec(at 25 ) could be achieved using ultra-thin SIMOX substrates, which is 6 times longer than that using the bulk substrate. A stacked capacitor cell with a PMOS cell transistor on an ultra-thin SIMOX substrate is very attractive and promising for future giga-bit DRAM cells.