IMAP: Integrated Memory Array Processor--Toward a GIPS Order SIMD Processing LSI--

Yoshihiro FUJITA; Nobuyuki YAMASHITA; Shin'ichiro OKAZAKI

IMAP: Integrated Memory Array Processor--Toward a GIPS Order SIMD Processing LSI--

Yoshihiro FUJITA, Nobuyuki YAMASHITA, Shin'ichiro OKAZAKI

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This paper describes the architecture and simulated performance of a proposed Integrated Memory Array Processor (IMAP). The IMAP is an LSI which integrates a large capacity memory and a one dimensional SIMD processor array on a single chip. The IMAP holds, in its on-chip memory, data which at the same time can be processed using a one dimensional SIMD processor integrated on the same chip. All processors can access their individual parts of memory columns at the same time. Thus, it has very high processor-memory data transfer bandwidth, and has no memory access bottleneck. Data stored in the memory can be accessed from outside of the IMAP via a conventional memory interface same as a VRAM. Since the SIMD processors on the IMAP are configured in a one dimensional array, multiple IMAPs could easily be connected in series to create a larger processor and memory configuration. To estimate the performance of such an IMAP, a system architecture and instruction set were first defined, and on the basis of those two, a simulator and an assembly language were then developed. In this paper, simulation results are presented which indicate the performance of an IMAP in both image processing and artificial neural network calculations.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.7 pp.1144-1150

Publication Date: 1993/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs)

Category: Memory-Based Parallel Processor Architectures

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Yoshihiro FUJITA, Nobuyuki YAMASHITA, Shin'ichiro OKAZAKI, "IMAP: Integrated Memory Array Processor--Toward a GIPS Order SIMD Processing LSI--" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 7, pp. 1144-1150, July 1993, doi: .
Abstract: This paper describes the architecture and simulated performance of a proposed Integrated Memory Array Processor (IMAP). The IMAP is an LSI which integrates a large capacity memory and a one dimensional SIMD processor array on a single chip. The IMAP holds, in its on-chip memory, data which at the same time can be processed using a one dimensional SIMD processor integrated on the same chip. All processors can access their individual parts of memory columns at the same time. Thus, it has very high processor-memory data transfer bandwidth, and has no memory access bottleneck. Data stored in the memory can be accessed from outside of the IMAP via a conventional memory interface same as a VRAM. Since the SIMD processors on the IMAP are configured in a one dimensional array, multiple IMAPs could easily be connected in series to create a larger processor and memory configuration. To estimate the performance of such an IMAP, a system architecture and instruction set were first defined, and on the basis of those two, a simulator and an assembly language were then developed. In this paper, simulation results are presented which indicate the performance of an IMAP in both image processing and artificial neural network calculations.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_7_1144/_p

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@ARTICLE{e76-c_7_1144,
author={Yoshihiro FUJITA, Nobuyuki YAMASHITA, Shin'ichiro OKAZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={IMAP: Integrated Memory Array Processor--Toward a GIPS Order SIMD Processing LSI--},
year={1993},
volume={E76-C},
number={7},
pages={1144-1150},
abstract={This paper describes the architecture and simulated performance of a proposed Integrated Memory Array Processor (IMAP). The IMAP is an LSI which integrates a large capacity memory and a one dimensional SIMD processor array on a single chip. The IMAP holds, in its on-chip memory, data which at the same time can be processed using a one dimensional SIMD processor integrated on the same chip. All processors can access their individual parts of memory columns at the same time. Thus, it has very high processor-memory data transfer bandwidth, and has no memory access bottleneck. Data stored in the memory can be accessed from outside of the IMAP via a conventional memory interface same as a VRAM. Since the SIMD processors on the IMAP are configured in a one dimensional array, multiple IMAPs could easily be connected in series to create a larger processor and memory configuration. To estimate the performance of such an IMAP, a system architecture and instruction set were first defined, and on the basis of those two, a simulator and an assembly language were then developed. In this paper, simulation results are presented which indicate the performance of an IMAP in both image processing and artificial neural network calculations.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - IMAP: Integrated Memory Array Processor--Toward a GIPS Order SIMD Processing LSI--
T2 - IEICE TRANSACTIONS on Electronics
SP - 1144
EP - 1150
AU - Yoshihiro FUJITA
AU - Nobuyuki YAMASHITA
AU - Shin'ichiro OKAZAKI
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1993
AB - This paper describes the architecture and simulated performance of a proposed Integrated Memory Array Processor (IMAP). The IMAP is an LSI which integrates a large capacity memory and a one dimensional SIMD processor array on a single chip. The IMAP holds, in its on-chip memory, data which at the same time can be processed using a one dimensional SIMD processor integrated on the same chip. All processors can access their individual parts of memory columns at the same time. Thus, it has very high processor-memory data transfer bandwidth, and has no memory access bottleneck. Data stored in the memory can be accessed from outside of the IMAP via a conventional memory interface same as a VRAM. Since the SIMD processors on the IMAP are configured in a one dimensional array, multiple IMAPs could easily be connected in series to create a larger processor and memory configuration. To estimate the performance of such an IMAP, a system architecture and instruction set were first defined, and on the basis of those two, a simulator and an assembly language were then developed. In this paper, simulation results are presented which indicate the performance of an IMAP in both image processing and artificial neural network calculations.
ER -