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Takayuki MORISHITA Youichi TAMURA Takami SATONAKA Atsuo INOUE Shin-ichi KATSU Tatsuo OTSUKI
We have developed a digital coprocessor with a dynamically reconfigurable pipeline architecture specified for a layered neural network which executes on-chip learning. The coprocessor attains a learning speed of 18 MCUPS that is approximately twenty times that of the conventional DSP. This coprocessor obtains expansibility in the calculation through a larger multi-layer, network by means of a network decomposition and a distributed processing approach.
Koji ARITA Eiji FUJII Yasuhiro SHIMADA Yasuhiro UEMOTO Masamichi AZUMA Shinichiro HAYASHI Toru NASU Atsuo INOUE Akihiro MATSUDA Yoshihisa NAGANO Shin-ich KATSU Tatsuo OTSUKI Gota KANO Larry D. McMILLAN Carlos A. Paz de ARAUJO
Characterization of silicon devices incorporating the capacitor which uses ferroelectric thin films as capacitor dielectrics is presented. As cases in point, a DRAM cell capacitor and an analog/digital silicon IC using the thin film of barium strontium titanate (Ba1-xSRxTiO3) are examined. Production and characterization of the ferroelectric thin films are also described, focusing on a Metal Organic Deposition technique and liquid source CVD.