We have developed a digital coprocessor with a dynamically reconfigurable pipeline architecture specified for a layered neural network which executes on-chip learning. The coprocessor attains a learning speed of 18 MCUPS that is approximately twenty times that of the conventional DSP. This coprocessor obtains expansibility in the calculation through a larger multi-layer, network by means of a network decomposition and a distributed processing approach.

A method for sweeping frequency ranges of over 130GHz within a tuning range of 30nm, without mode hopping, has been realized. The optical frequency is swept with a fine translation-rotation grating drive which uses a new, simplified operation method and a thermally controlled semiconductor laser system.

We have developed a 64-neuron electrically trainable BiCMOS analog neuroprocessor based on 3-layered PDP networks with a feedforward time as short as 10 µs which is equivalent to the operation speed as high as 108 multiplications per second. A crucial point in this development is application of a dynamic refreshment technique to a weighting circuit. A sufficiently long retention time of the synapse weight has thereby been attained, leading to a practical operation of the neuroprocessor.