Gold nanoparticles (GNPs) are often used as island electrodes of single-electron (SE) devices. One of technical challenges in fabrication of SE devices with GNPs is the placement of GNPs in a nanogap between two lead electrodes. Utilization of dielectrophoresis (DEP) phenomena is one of possible solutions for this challenge, whereas the fabrication process with DEP includes stochastic aspects. In this brief paper, we present our experimental results on electric resistance of GNP arrays assembled by DEP. More than 300 pairs of electrodes were investigated under various DEP conditions by trial and error approach. We evaluated the relationship between the DEP conditions and the electric resistance of assembled GNP arrays, which would indicate possible DEP conditions for fabrication of SE devices.

A fully integrated 5.8 GHz ETC transceiver LSI has been developed. The transceiver consists of LNA, down-conversion MIX, ASK detector, ASK modulator, DA VCO, and ΔΣ-fractional-N PLL. The features of the transceiver are integrated matching circuitry for LNA input and for DA output, ASK modulator with VGA for local signal control to avoid local leakage and to keep suitable modulation index, and LO circuitry consisting of ΔΣ-fractional-N PLL and interference-robust ∞-shape inductor VCO to diminish magnetic coupling from any other circuitry. Use of these techniques enabled realization of the input and output VSWR of less than 1.25, modulation index of over 95%, and enough qualified TX signals. This transceiver was manufactured by 1P3M SiGe-BiCMOS process with 47 GHz cut-off frequency.

Copper contamination behavior is studied, depending on the pH level, conductivity type P or N of a silicon substrate, and contamination method of copper. If the pH level of a copper containing solution is adjusted by using ammonia, copper atoms and ammonia molecules produce copper ion complexes. Accordingly, the amount of copper adsorption on the substrate surface is decreased. When N-type silicon substrates are contaminated by means of copper containing solutions, copper atoms on the surfaces diffuse into bulk crystal even at room temperature. But for P-type silicon substrates, copper atoms are transferred into bulk crystal only after high temperature annealing. In the case of silicon substrates contaminated by contact with metallic copper, no copper atom diffusion into bulk crystal was observed. The above mentioned copper contamination behavior can be explained by the charge transfer interaction of copper atoms with silicon substrates.

This paper describes a 0.8-µm CMOS LSI developed for a 156-Mb/s serial interface in ATM switching systems. Recently, there have been increasing problems of connector pin neck and higher power consumption when enhancing switching system capacity. To overcome these problems, we have developed an LSI with a high-speed interface by using CMOS technology to achieve low power consumption. A low-swing differential signal level is used to achieve 156-Mb/s data transmission. We named this new circuit technique ALTS (Advanced Low-level Transmission circuit System). Using the LSI, transmission can be achieved between boards or racks through a 10-meter twisted pair cable. The LSI has a 156-Mb/s transmitter-receiver, a serial-to-parallel converter and a parallel-to-serial converter. It performs 19.5-Mb/s parallel data/156-Mb/s serial data conversion and 156-Mb/s serial data transmission. In addition, it has a bit phase synchronizer and cell synchronizer, which enables it to transmit and synchronize serial data without a paralleled clock or a paralleled cell top signal, by distributing a common 156-MHz clock and a common cell top signal to the whole system. We evaluated the bit error rate and timing margin on data transmission under several conditions. The results show that we can apply this LSI to commercially available ATM switching systems. This paper also describes methods of expanding switch capacity and transmitting 624-Mb/s data using this LSI.