Material research on capacitor dielectrics for DRAM applications is reviewed. The state of the art technologies to prepare Si3N4,Ta2O5, and SrTiO3 thin films for capacitors are described. The down-scaling limits for Si3N4 and Ta2O5 capacitors seem to be 3.5 and 1.5 nm SiO2 equivalent thickness, respectively. Combined with a rugged polysilicon electrode surface,Si3N4 and Ta2O5 based-capacitors are available for 256 Mbit and 1 Gbit DRAMs. At the present time, the minimum SiO2 equivalent thickness for high permittivity materials is around 1 nm with the leakage current density of 10-7 A/cm2. Among the great variety of ferroelectrics, two families of materials,i.e., Pb (Zr, Ti) O3 and (Ba, Sr) TiO3 have emerged as the most promising candidates for 1 Gbit DRAMs and beyond. If the chemical vapor deposition technology can be established for these materials, capacitor dielectrics should not be a limiting issue for Gbit DRAMs.

A contact-less cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim (F-N) tunneling, has been developed for single 3 V power-supply 64 Mbit and future flash memories. A 1.50 µm2 cell area is obtained by using 0.4 µm technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) an advanced rapid thermal process for 7.5 nm-thick tunnel-oxynitride. The internal-voltages used for PROGRAM and ERASE are8 V and 12 V, respectively. The use of low positive internal-voltages results in reducing total process step numbers compared with reported memory cells. The HiCR cell also realizes low power and fast random access with a single 3 V power-supply.

This paper describes the formation of ultra-thin tantalum oxide capacitors, using rapid thermal nitridation (RTN) of the storage-node polycrystalline-silicon surface prior to low-pressure chemical vapor deposition of tantalum oxide, using penta-ethoxy-tantalum [(Ta(OC2H5)5) and oxygen gas mixture. The films are annealed at 600-900 in dry O2 atmosphere. Densification of the as-deposited film by annealing in dry O2 is indispensable to the formation of highly reliable ultra-thin tantalum oxide capacitors. The RTN treatment reduces the SiO2 equivalent thickness and leakage current of the tantalum oxide film, and improves the time dependent dielectric breakdown characteristics of the film.

Copper contamination behavior is studied, depending on the pH level, conductivity type P or N of a silicon substrate, and contamination method of copper. If the pH level of a copper containing solution is adjusted by using ammonia, copper atoms and ammonia molecules produce copper ion complexes. Accordingly, the amount of copper adsorption on the substrate surface is decreased. When N-type silicon substrates are contaminated by means of copper containing solutions, copper atoms on the surfaces diffuse into bulk crystal even at room temperature. But for P-type silicon substrates, copper atoms are transferred into bulk crystal only after high temperature annealing. In the case of silicon substrates contaminated by contact with metallic copper, no copper atom diffusion into bulk crystal was observed. The above mentioned copper contamination behavior can be explained by the charge transfer interaction of copper atoms with silicon substrates.