1-2hit |
Ken-ichi OYAMA Noriaki KODAMA Hiroki SHIRAI Kenji SAITOH Yosiaki S. HISAMUNE Takeshi OKAZAWA
A 0.4 µm stacked gate cell for a 64 Mbit flash memory has been developed which has the Symmetrical Side Wall Diffusion Self Aligned (SSW-DSA) structure. Using the proposed SSW-DSA cell with p+ pockets at both the drain and the source, and adequate punchthrough resistance to scale the gate length down to sub-half-micron has been obtained. It is also demonstrated that the channel erasing scheme applying negative bias to the gate, which is adopted for the SSW-DSA cell, shows lower trapped charges after Write/Erase (W/E) cycles evaluated by a charge pumping technique, and results in better endurance an retention characteristics than conventional erasing schemes.
Kohji KANAMORI Yosiaki S. HISAMUNE Taishi KUBOTA Yoshiyuki SUZUKI Masaru TSUKIJI Eiji HASEGAWA Akihiko ISHITANI Takeshi OKAZAWA
A contact-less cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim (F-N) tunneling, has been developed for single 3 V power-supply 64 Mbit and future flash memories. A 1.50 µm2 cell area is obtained by using 0.4 µm technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) an advanced rapid thermal process for 7.5 nm-thick tunnel-oxynitride. The internal-voltages used for PROGRAM and ERASE are8 V and 12 V, respectively. The use of low positive internal-voltages results in reducing total process step numbers compared with reported memory cells. The HiCR cell also realizes low power and fast random access with a single 3 V power-supply.