IEICE TRANSACTIONS on Electronics
A High Capacitive Coupling Ratio (HiCR) Cell for Single 3 Volt Power Supply Flash Memories
Summary :
A contact-less cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim (F-N) tunneling, has been developed for single 3 V power-supply 64 Mbit and future flash memories. A 1.50 µm2 cell area is obtained by using 0.4 µm technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) an advanced rapid thermal process for 7.5 nm-thick tunnel-oxynitride. The internal-voltages used for PROGRAM and ERASE are
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.8 pp.1296-1302
- Publication Date
- 1994/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
- Category
- Non-volatile Memory
Authors
Kohji KANAMORI
Yosiaki S. HISAMUNE
Taishi KUBOTA
Yoshiyuki SUZUKI
Masaru TSUKIJI
Eiji HASEGAWA
Akihiko ISHITANI
Takeshi OKAZAWA
Keyword
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Kohji KANAMORI, Yosiaki S. HISAMUNE, Taishi KUBOTA, Yoshiyuki SUZUKI, Masaru TSUKIJI, Eiji HASEGAWA, Akihiko ISHITANI, Takeshi OKAZAWA, "A High Capacitive Coupling Ratio (HiCR) Cell for Single 3 Volt Power Supply Flash Memories" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 8, pp. 1296-1302, August 1994, doi: .
Abstract: A contact-less cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim (F-N) tunneling, has been developed for single 3 V power-supply 64 Mbit and future flash memories. A 1.50 µm2 cell area is obtained by using 0.4 µm technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) an advanced rapid thermal process for 7.5 nm-thick tunnel-oxynitride. The internal-voltages used for PROGRAM and ERASE are
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_8_1296/_p
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@ARTICLE{e77-c_8_1296,
author={Kohji KANAMORI, Yosiaki S. HISAMUNE, Taishi KUBOTA, Yoshiyuki SUZUKI, Masaru TSUKIJI, Eiji HASEGAWA, Akihiko ISHITANI, Takeshi OKAZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High Capacitive Coupling Ratio (HiCR) Cell for Single 3 Volt Power Supply Flash Memories},
year={1994},
volume={E77-C},
number={8},
pages={1296-1302},
abstract={A contact-less cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim (F-N) tunneling, has been developed for single 3 V power-supply 64 Mbit and future flash memories. A 1.50 µm2 cell area is obtained by using 0.4 µm technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) an advanced rapid thermal process for 7.5 nm-thick tunnel-oxynitride. The internal-voltages used for PROGRAM and ERASE are
keywords={},
doi={},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - A High Capacitive Coupling Ratio (HiCR) Cell for Single 3 Volt Power Supply Flash Memories
T2 - IEICE TRANSACTIONS on Electronics
SP - 1296
EP - 1302
AU - Kohji KANAMORI
AU - Yosiaki S. HISAMUNE
AU - Taishi KUBOTA
AU - Yoshiyuki SUZUKI
AU - Masaru TSUKIJI
AU - Eiji HASEGAWA
AU - Akihiko ISHITANI
AU - Takeshi OKAZAWA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1994
AB - A contact-less cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim (F-N) tunneling, has been developed for single 3 V power-supply 64 Mbit and future flash memories. A 1.50 µm2 cell area is obtained by using 0.4 µm technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) an advanced rapid thermal process for 7.5 nm-thick tunnel-oxynitride. The internal-voltages used for PROGRAM and ERASE are
ER -
English
