A Symmetrical Side Wall (SSW)-DSA Cell and the Channel Erasing Scheme for a 64 Mbit Flash Memory
Summary :
A 0.4 µm stacked gate cell for a 64 Mbit flash memory has been developed which has the Symmetrical Side Wall Diffusion Self Aligned (SSW-DSA) structure. Using the proposed SSW-DSA cell with p+ pockets at both the drain and the source, and adequate punchthrough resistance to scale the gate length down to sub-half-micron has been obtained. It is also demonstrated that the channel erasing scheme applying negative bias to the gate, which is adopted for the SSW-DSA cell, shows lower trapped charges after Write/Erase (W/E) cycles evaluated by a charge pumping technique, and results in better endurance an retention characteristics than conventional erasing schemes.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.11 pp.1358-1363
- Publication Date
- 1992/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on LSI Memories)
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Ken-ichi OYAMA, Noriaki KODAMA, Hiroki SHIRAI, Kenji SAITOH, Yosiaki S. HISAMUNE, Takeshi OKAZAWA, "A Symmetrical Side Wall (SSW)-DSA Cell and the Channel Erasing Scheme for a 64 Mbit Flash Memory" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 11, pp. 1358-1363, November 1992, doi: .
Abstract: A 0.4 µm stacked gate cell for a 64 Mbit flash memory has been developed which has the Symmetrical Side Wall Diffusion Self Aligned (SSW-DSA) structure. Using the proposed SSW-DSA cell with p+ pockets at both the drain and the source, and adequate punchthrough resistance to scale the gate length down to sub-half-micron has been obtained. It is also demonstrated that the channel erasing scheme applying negative bias to the gate, which is adopted for the SSW-DSA cell, shows lower trapped charges after Write/Erase (W/E) cycles evaluated by a charge pumping technique, and results in better endurance an retention characteristics than conventional erasing schemes.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_11_1358/_p
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@ARTICLE{e75-c_11_1358,
author={Ken-ichi OYAMA, Noriaki KODAMA, Hiroki SHIRAI, Kenji SAITOH, Yosiaki S. HISAMUNE, Takeshi OKAZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Symmetrical Side Wall (SSW)-DSA Cell and the Channel Erasing Scheme for a 64 Mbit Flash Memory},
year={1992},
volume={E75-C},
number={11},
pages={1358-1363},
abstract={A 0.4 µm stacked gate cell for a 64 Mbit flash memory has been developed which has the Symmetrical Side Wall Diffusion Self Aligned (SSW-DSA) structure. Using the proposed SSW-DSA cell with p+ pockets at both the drain and the source, and adequate punchthrough resistance to scale the gate length down to sub-half-micron has been obtained. It is also demonstrated that the channel erasing scheme applying negative bias to the gate, which is adopted for the SSW-DSA cell, shows lower trapped charges after Write/Erase (W/E) cycles evaluated by a charge pumping technique, and results in better endurance an retention characteristics than conventional erasing schemes.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A Symmetrical Side Wall (SSW)-DSA Cell and the Channel Erasing Scheme for a 64 Mbit Flash Memory
T2 - IEICE TRANSACTIONS on Electronics
SP - 1358
EP - 1363
AU - Ken-ichi OYAMA
AU - Noriaki KODAMA
AU - Hiroki SHIRAI
AU - Kenji SAITOH
AU - Yosiaki S. HISAMUNE
AU - Takeshi OKAZAWA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1992
AB - A 0.4 µm stacked gate cell for a 64 Mbit flash memory has been developed which has the Symmetrical Side Wall Diffusion Self Aligned (SSW-DSA) structure. Using the proposed SSW-DSA cell with p+ pockets at both the drain and the source, and adequate punchthrough resistance to scale the gate length down to sub-half-micron has been obtained. It is also demonstrated that the channel erasing scheme applying negative bias to the gate, which is adopted for the SSW-DSA cell, shows lower trapped charges after Write/Erase (W/E) cycles evaluated by a charge pumping technique, and results in better endurance an retention characteristics than conventional erasing schemes.
ER -
English
