A fully integrated 5.8 GHz ETC transceiver LSI has been developed. The transceiver consists of LNA, down-conversion MIX, ASK detector, ASK modulator, DA VCO, and ΔΣ-fractional-N PLL. The features of the transceiver are integrated matching circuitry for LNA input and for DA output, ASK modulator with VGA for local signal control to avoid local leakage and to keep suitable modulation index, and LO circuitry consisting of ΔΣ-fractional-N PLL and interference-robust ∞-shape inductor VCO to diminish magnetic coupling from any other circuitry. Use of these techniques enabled realization of the input and output VSWR of less than 1.25, modulation index of over 95%, and enough qualified TX signals. This transceiver was manufactured by 1P3M SiGe-BiCMOS process with 47 GHz cut-off frequency.

A new approach to the analysis of large-scale thermal system has been developed, in which the thermal resistance matrix of principal portions of the system can be computed very quickly. The features of this method are 1) approximation of rectangular heat sources by equivalent circular ones, 2) formulation of a thermal equation under condition that the semiconductor chip extends infinitely, and 3) modification for a finite chip using the image method, upon necessity. In this paper, formulation and discussions of the present method are described with applications to the thermal problems for high-frequency power transistors that are divided in a large number of cellular devices. Using the present method, isothermal design and thermal instability phenomena such as hot spots and current crowdings are studied.

Limitations, innovations, and challenges of circuits and devices in silicon integrated circuits when they are scaled down to a half micrometer and smaller and reviewed. At the start, by examining physical limits of signal processing capabilities of a semiconductor device and power limits of circuits, the major directions of innovations are given. Then, device innovations in advanced MOSFET devices featuring sizes of a half micrometer, quarter micrometer, and even smaller than one tenth of a micrometer are reviewed. Circuit innovations in MOS VLSI's are also reviewed. Major issues are signal-to-noise ratio and speed of operation at low supply voltages. It is pointed out that miniaturized MOSFET's with channel lengths even shorter than one tenth of a micrometer could probably be realized with superior performance, but the circuit technique of using them at low-voltage power supplies still remains a challenge. Finally, it is pointed out that the real challenges in the future will be design and test limits of huge systems, and the real goals of engineers in the future will be functional integration rather than scale integration.

This paper describes an automatic transistor model parameter generation technique for a circuit simulator which can take device geometry into account. An 'area factor' is used to generate model parameters for different transistor shapes; however, the conventional method could not reflect the actual geometry differences other than for the emitter area. This resulted in inaccurate model parameters and such parameters were not acceptable to accurately simulate circuits for RF ICs. The proposed technique uses actually measured parameters and process data for a reference transistor and generates the individual model parameters for different shape transistors. In this technique, the parasitic resistor values are calculated and fitted in place of directly extracting them from the measured data. This ensures a better estimate. The reference transistor is made sufficiently large to neglect measurement errors in generating the parasitic capacitors. Thus, the model parameters for a very small transistor can be generated accurately. The model generating procedure has been implemented as a pre-processor to SPICE. This technique enables a fast turn around for RF IC circuit design which uses various shape transistors.