IEICE TRANSACTIONS on Electronics
Multiple-Valued Static Random-Access-Memory Design and Application
Summary :
In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E76-C No.3 pp.403-411
- Publication Date
- 1993/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
- Category
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Zheng TANG, Okihiko ISHIZUKA, Hiroki MATSUMOTO, "Multiple-Valued Static Random-Access-Memory Design and Application" in IEICE TRANSACTIONS on Electronics,
vol. E76-C, no. 3, pp. 403-411, March 1993, doi: .
Abstract: In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_3_403/_p
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@ARTICLE{e76-c_3_403,
author={Zheng TANG, Okihiko ISHIZUKA, Hiroki MATSUMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Multiple-Valued Static Random-Access-Memory Design and Application},
year={1993},
volume={E76-C},
number={3},
pages={403-411},
abstract={In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Multiple-Valued Static Random-Access-Memory Design and Application
T2 - IEICE TRANSACTIONS on Electronics
SP - 403
EP - 411
AU - Zheng TANG
AU - Okihiko ISHIZUKA
AU - Hiroki MATSUMOTO
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1993
AB - In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.
ER -
English
