High-Speed Digital Circuit for Discrete Cosine Transform
Summary :
This paper deals with a high-speed digital circuit for discrete cosine transform (DCT). We propose a new algorithm that reduces the number of calculations for partial sum-of-products in the DCT and synthesize the small gate depth circuit of DCT by using carry-propagation-free adders based on redundant binary {
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E78-A No.8 pp.957-962
- Publication Date
- 1995/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Digital Signal Processing)
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Motonobu TONOMURA, "High-Speed Digital Circuit for Discrete Cosine Transform" in IEICE TRANSACTIONS on Fundamentals,
vol. E78-A, no. 8, pp. 957-962, August 1995, doi: .
Abstract: This paper deals with a high-speed digital circuit for discrete cosine transform (DCT). We propose a new algorithm that reduces the number of calculations for partial sum-of-products in the DCT and synthesize the small gate depth circuit of DCT by using carry-propagation-free adders based on redundant binary {
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e78-a_8_957/_p
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@ARTICLE{e78-a_8_957,
author={Motonobu TONOMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Speed Digital Circuit for Discrete Cosine Transform},
year={1995},
volume={E78-A},
number={8},
pages={957-962},
abstract={This paper deals with a high-speed digital circuit for discrete cosine transform (DCT). We propose a new algorithm that reduces the number of calculations for partial sum-of-products in the DCT and synthesize the small gate depth circuit of DCT by using carry-propagation-free adders based on redundant binary {
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - High-Speed Digital Circuit for Discrete Cosine Transform
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 957
EP - 962
AU - Motonobu TONOMURA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E78-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 1995
AB - This paper deals with a high-speed digital circuit for discrete cosine transform (DCT). We propose a new algorithm that reduces the number of calculations for partial sum-of-products in the DCT and synthesize the small gate depth circuit of DCT by using carry-propagation-free adders based on redundant binary {
ER -
English
