A novel method is presented for designing discrete coeffcient FIR linear phase filters using Hopfield neural networks. The proposed method is based on the minimization of the energy function of Hopfield neural networks. In the proposed method, the optimal solution for each filter gain factor is first searched for, then the optimal filter gain factor is selected. Therefore, a good solution in the specified criterion can be obtained. The feature of the proposed method is that it can be used to design FIR linear phase filters with different criterions simultaneously. A design example is presented to demonstrate The effectiveness of the proposed method.

Improvement of the convergence characteristics of the NLMS algorithm has received attention in the area of adaptive filtering. A new variable stepsize NLMS method, in which the stepsize is updated optimally by using variances of the measured error signal and the estimated noise, is proposed. The optimal control equation of the stepsize has been derived from a convergence characteristic approximation. A new condition to judge convergence is introduced in this paper to ensure the fastest initial convergence speed by providing precise timing to start estimating noise level. And further, some adaptive smoothing devices have been added into the ADF to overcome the saturation problem of the identification error caused by some random deviations. By the simulation, The initial convergence speed and the identification error in precise identification mode is improved significantly by more precise adjustment of stepsize without increasing in computational cost. The results are the best ever reported performanced. This variable stepsize NLMS-ADF also shows good effectiveness even in severe conditions, such as noisy or fast changing circumstances.

This paper proposes a modified normalized LMS algorithm based on a long-term average of the reference input signal power. The reference input signal power for normalization is estimated by using two leaky integrators with a short and a long time constants. Computer simulation results compare the performance of the proposed algorithm with some previosuly proposed adaptive-step algorithms. The proposed algorithm converges faster than the conventional adaptive-step algorithms. Almost 30dB of the ERLE (Echo Return Loss Enhancement), which is comparable to the conventional algorithms, is achieved in noisy environments.

An adaptive digital filter with adaptive sampling phase is proposed. The structure of the filter makes use of an adaptive delay device at the input of the filter. The algorithm is derived to determine the value of the delay and the filter coefficients by minimizing MSE (mean square error) between the desired signal and the filter output. The computer simulation of the convergence of the proposed adaptive filter with the input of sinusoidal wave and BPSK modulated wave are shown. According to the simulation, the MSE of the proposed adaptive delay algorithm is lower than that of the conventional LMS algorithm.

This paper describes modifications to a previously proposed 8-kb/s 4-ms-delay CELP speech coding algorithm with a view to improving the speech quality while maintaining low delay and only moderately increasing complexity. The modifications are intended to improve the effectiveness of interframe pitch lag prediction and the sub-optimality level of the excitation coding to the backward adapted synthesis filter by using delayed decision and joint optimization techniques. Results of subjective listening tests using Japanese speech indicate that the coded speech quality is significantly superior to that of the 8-kb/s VSELP coder which has a 20-ms delay. A method that reduces the computational complexity of closed-loop 3-tap pitch prediction with no perceptible degradation in speech quality is proposed, based on representing the pitch-tap vector as the product of a scalar pitch gain and a normalized shape codevector.

In this paper, we propose two parallel processing methods for multidimensional (MD) sampling lattice alteration. The use of our proposed methods enables us to alter the sampling lattice of a given MD signal sequence in parallel without any redundancy caused by up- and down-sampling, even if the alteration is rational and non-separable. Our proposed methods are provided by extending two conventional block processing techniques for FIR filtering: the overlap-add method and the overlap-save method. In these proposed methods, firstly a given signal sequence is segmented into some blocks, secondly sampling lattice alteration is implemented for each block data individually, and finally the results are fitted together to obtain the output sequence which is identical to the sequence obtained from the direct sampling lattice alteration. Besides, we provide their efficient implementation: the DFT-domain approach, and give some comments on the computational complexity in order to show the effectiveness of our proposed methods.

This paper presents a simple and efficient method for estimation of parameters useful for textured image analysis. On the basia of a 2-D Wold-like decomposition of homogenenous random fields, the texture field can be decomposed into a sum of two mutually orthogonal components: a deterministic component and an indeterministic component. The spectral density function (SDF) of the former is a sum of 1-D or 2-D delta functions. The 2-D autocorrelation function (ACF) of the latter is fitted to the assumed anisotropic ACF that has an elliptical contour. The parameters representing the ellipse and those representing the delta functions can be used to detect rotation angles and scaling factors of test textures. Specially, rotation and scaling invariant parameters, which are applicable to the classification of rotated and scaled textured images, can be estimated by combining these parameters. That is, a test texture can be correctly classified even if it is rotated and scaled. Several computer experiments on natural textures show the effectiveness of this method.

This paper proposes a human interface where a novel input method is used to substitute conventional input devices. It overcomes the deficiencies of physical devices, as it is based on image processing techniques. The proposed interface is composed of three parts: extraction of a person's handshape from a digitized image, detection of its fingertip, and interpretation by a software application. First, images of a pointing hand are digitized to obtain a sequence of monochrome frames. In each frame the hand is isolated from the background by means of gray-level slicing; with threshold values calculated dynamically by the combination of movement detection and histogram analysis. The advantage of this approach is that the system adapts itself to any user and compensates any changes in the illumination, while in conventional methods the threshold values are previously defined or markers have to be attached to the hand in order to give reference points. Second, once the hand is isolated, fingertip coordinates are extracted by scanning the image. Third, the coordinates are inputted to an application interface. Overall, as the algorithms are simple and only monochrome images are used, the amount of processing is kept low, making this system suitable to real-time processing without needing expensive hardware.

This paper deals with a high-speed digital circuit for discrete cosine transform (DCT). We propose a new algorithm that reduces the number of calculations for partial sum-of-products in the DCT and synthesize the small gate depth circuit of DCT by using carry-propagation-free adders based on redundant binary {1,0,1} representation. The gate depth is only half to one third that of the conventional algorithms with the same number of gates.

This paper presents a newly developed architecture for a highly parallel DSP suited for realtime image reaognition. The programmable DSP was designed for a variety of image recognition systems, such as computer vision systems, character recognition systems and others. The DSP consists of functional units suited for image recognition: a SIMD processing core, a hierarchical bus, an Address Generation Unit, Data Memories, a DMA controller, a Link Unit, and a Control Unit. The high performance of 3.2GOPS is realized by the eight-parallel SIMD core with a optimized pipeline structure for image recognition algorithms. The DSP supports flexible data transfers including an extraction of lacal images from raster scanned image data, a table-loop-up, a data-broadcasting, and a data-shifting among processing units in the SIMD core, for effective execution of various image processing algorithms. Hence, the DSP can process a 55 spatial filtering for 512512 images within 13.1 msec. Adopting the DSP to a Japanese character recognition system, the speed of 924 characters/sec can be achieved for feature extractions and feature vectors matchings. The DSP can be integrated in a 14.514.5 mm² single-chip, using 0.5 µm CMOS technology. In this paper, the key features of the architecture and the new techniques enabling efficient operation of the eight parallel processing units are described. Estimation of the performance of the DSP is also presented.

A down sampling technique was applied to signal processing of fiber optic gyroscopes with optical phase modulation. The technique shifts the frequency spectrum of the gyroscopic signal down to low frequencies, and lowers the speed requirements for analog-to-digital (A/D) conversion and numerical operations. A single-chip digital signal processor (DSP) with a built-in A/D converter and timers was used to demonstrate the proposed technique. The DSP internally generated a phase modulation signal and sampling trigger timing. The reference signals for digital lock-in discrimination of gyroscopic spectrum are generated by using an external binary counter, and their phases were adjusted optimally by DSP software. The DSP compensated for fluctuations in laser source intensity and phase modulation index, using the signal spectrum extracted, and linearized the gyroscopic response. The measured resolution of rotation detection was 0.9 deg/s (with a full scale of 100 deg/s) and it agreed with the resolution in A/D conversion.

This paper described discrete time Cellular Neural Networks (DT-CNN) with two types of neuron circuits for image coding from an analog format to a digital format and their VLSI implementations. The image coding methods proposed in this paper have been investigated for a purpose of transmission of a coded image and restoration again without a large loss of an original image information. Each neuron circuti of a network receives one pixel of an input image, and processes it with binary outputs data fed from neighboring neuron circuits. Parallel dynamics quantization methods have been adopted for image coding methods. They are performed in networks to decide an output binary value of each neuron circuit according to output values of neighboring neuron circuits. Delayed binary outputs of neuron circuits in a neighborhood are directly connected to inputs of a current active neuron circuit. Next state of a network is computed form a current state at some neuron circuits in any time interval. Models of two types of neuron circuits and networks are presented and simulated to confirm an ability of proposed methods. Also, physical layout designs of coding chips have been done to show their possibility of VLSI realizations.

A description language for matrix and vector expressions and its compiler for DSPs are shown. They provide both a user-friendly programming environment and efficient codes. In order to increase throughput and to reduce amount of methods based on mathematical laws are introduced. A method to decide the matrix and vector storage location suitable for processing on DSP is also proposed.

This paper describes a system that can enchance the speech quality degradation due to severe band limitation during speech transmission. We have already proposed a spectrum widening method that utilizes aliasing in sampling rate conversion and digital filtering for spectrum shaping. This paper proposes a new method that offers improved performance in terms of the spectrum distortion characteristics. Implementation procedures are clarified, and its performance is discussed. The proposed method can effectively enhance speech quality.

In this letter, we introduce a predictor based least square (PLS) algorithm. By involving both order- and time-update recursions, the PLS algorithm is found to have a more stable performance compared with the stable version (Version II) of the RLS algorithm shown in Ref.[1]. Nevertheless, the computational requirement is about 50% of that of the RLS algorithm. As an application, the PLS algorithm can be applied to the fast Newton transversal filters (FNTF). The FNTF algorithms suffer from the numerical instability problem if the quantities used for extending the gain vector are computed by using the fast RLS algorithms. By combing the PLS and the FNTF algorithms, we obtain a much more stable performance and a simple algorithm formulation.

A new variable step size Least Mean Square (LMS) FIR adaptive filter algorithm (VSS-CC) is proposed. In the VSS-CC algorithm the step size adjustment (α) is controlled by using the correlation between the output error (e(n)) and the adaptive filter output ((n)). At small times, e(n) and (n) are correlated which will cause a large α providing faster tracking. When the algorithm converges, the correlation will result in a small size α to yield smaller misadjustments. Computer simulations show that the proposed VSS-CC algori thm achieves a better Echo Return Loss Enhancemen (ERLE) than a conventional NLMS Algorithm. The VSS-CC algorithm was also compared with another variable step algorithm, achieving the VSS-CC a better ERLE when the additive noise is incremented.

In this paper, we discuss design of quadrature mirror filter (QMF) banks using digital allpass networks in the frequency domain. In the QMF banks composed of a parallel connection of two allpass networks, both aliasing error and amplitude distortion are always completely canceled. Therefore, we only need to design the analysis filters and eliminate phase distortion of the overall transfer function. We consider design of the QMF banks in two cases where phase responses of the filters are repuired or not required. In the case where the phase responses are not required, the design problem can be reduced to design of phase difference of two allpass networks. In the case where the phase responses are required, we present a procedure for designing the QMF banks with both equiripple magnitude and phase responses.

The most creative tasks in synthesizing pipelined data paths executing software descriptions are determinations of latency and stage of pipeline, operation scheduling and hardware allocation. They are interrelated closely and depend on each other; thus finding its optimal solution has been a hard problem so far. By using simulated annealing methodology, these three tasks can be formulated as a three dimensional placement problem of operations in stage, time step and functional units space. This paper presents an efficient method based on simulated annealing to provide excellent solutions to the problem of not only the determinations of latency and stage of pipeline, operation scheduling and hardware allocation simultaneously, but also the pipelined data path synthesis under the constraints of performance or hardware cost. It is able to find a near optimal latency and stage of pipeline, an operation schedule and a hardware allocation in a reasonable time, while effectively exploring the existing tradeoffs in the design space.

This paper condiders a problem of logecal configuration in reconfigurable VCDN (Virtual Circuit Data Networks) which is analyzed through a mimimax approach, and its objective is to minimize the largest delay on any logical link, measured in both queueing delay and propagation delay. The problem is formulated as a 0/1 mixed integer programming and analyzed by decomposing it into two subproblems, called routing and dimensioning problems, for which an efficient hauristic algorithm is proposed in an iterating process made beween the two subproblems for solution improvement. The algorithm is tested for its performance eveluation.

A multi-dimensional shaping scheme based on multi-level Maximum Average Weight (MAW)-codes is presented. One can reduce the average energy of transmitted signal, by using low energy signal points more frequently than high energy ones. The proposed scheme employs a multi-dimensional region of 2,4,6 and 8 dimensions; these regions are selected using a multi-level MAW-code. A multi-level MAW-code is a q-ary code and has unequal probability of the occurrence of a symbol. The scheme can achieve a shaping gain of 0.6-1.0 dB with small constellation expansion ratio and peak to average energy ratio. This scheme is based on a two-level table look up algorithm. Therefore, the less complexity of encoding/decoding can be realized.

Spectrum scrambling can be applied in vehicle telephones for more secure communication. This letter shows a spectrum scrambling method using real coefficients M band uniform QMF banks. Once QMF banks are designed, spectrum scrambling filters can be realized with simpler procedures. By introducing selectors in the filters, the scrambling scheme may be easily varied in real time processing. Design examples and experimental simulations are included.

An error correction/detection decoding scheme of binary Hamming codes is proposed. Error correction is performed by algebraic decoding and then error detection is performed by simple likelihood ratio testing. The proposed scheme reduces the probability of undetected decoding error in comparison with conventional error correction scheme and increases throughjput in comparison with conventional error detection scheme.