A Highly Parallel DSP Architecture for Image Recognition

Hiroyuki KAWAI; Yoshitsugu INOUE; Rebert STREITENBERGER; Masahiko YOSHIMOTO

A Highly Parallel DSP Architecture for Image Recognition

Hiroyuki KAWAI, Yoshitsugu INOUE, Rebert STREITENBERGER, Masahiko YOSHIMOTO

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This paper presents a newly developed architecture for a highly parallel DSP suited for realtime image reaognition. The programmable DSP was designed for a variety of image recognition systems, such as computer vision systems, character recognition systems and others. The DSP consists of functional units suited for image recognition: a SIMD processing core, a hierarchical bus, an Address Generation Unit, Data Memories, a DMA controller, a Link Unit, and a Control Unit. The high performance of 3.2GOPS is realized by the eight-parallel SIMD core with a optimized pipeline structure for image recognition algorithms. The DSP supports flexible data transfers including an extraction of lacal images from raster scanned image data, a table-loop-up, a data-broadcasting, and a data-shifting among processing units in the SIMD core, for effective execution of various image processing algorithms. Hence, the DSP can process a 55 spatial filtering for 512512 images within 13.1 msec. Adopting the DSP to a Japanese character recognition system, the speed of 924 characters/sec can be achieved for feature extractions and feature vectors matchings. The DSP can be integrated in a 14.514.5 mm² single-chip, using 0.5 µm CMOS technology. In this paper, the key features of the architecture and the new techniques enabling efficient operation of the eight parallel processing units are described. Estimation of the performance of the DSP is also presented.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E78-A No.8 pp.963-970

Publication Date: 1995/08/25

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Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing)

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Hiroyuki KAWAI, Yoshitsugu INOUE, Rebert STREITENBERGER, Masahiko YOSHIMOTO, "A Highly Parallel DSP Architecture for Image Recognition" in IEICE TRANSACTIONS on Fundamentals, vol. E78-A, no. 8, pp. 963-970, August 1995, doi: .
Abstract: This paper presents a newly developed architecture for a highly parallel DSP suited for realtime image reaognition. The programmable DSP was designed for a variety of image recognition systems, such as computer vision systems, character recognition systems and others. The DSP consists of functional units suited for image recognition: a SIMD processing core, a hierarchical bus, an Address Generation Unit, Data Memories, a DMA controller, a Link Unit, and a Control Unit. The high performance of 3.2GOPS is realized by the eight-parallel SIMD core with a optimized pipeline structure for image recognition algorithms. The DSP supports flexible data transfers including an extraction of lacal images from raster scanned image data, a table-loop-up, a data-broadcasting, and a data-shifting among processing units in the SIMD core, for effective execution of various image processing algorithms. Hence, the DSP can process a 55 spatial filtering for 512512 images within 13.1 msec. Adopting the DSP to a Japanese character recognition system, the speed of 924 characters/sec can be achieved for feature extractions and feature vectors matchings. The DSP can be integrated in a 14.514.5 mm² single-chip, using 0.5 µm CMOS technology. In this paper, the key features of the architecture and the new techniques enabling efficient operation of the eight parallel processing units are described. Estimation of the performance of the DSP is also presented.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e78-a_8_963/_p

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@ARTICLE{e78-a_8_963,
author={Hiroyuki KAWAI, Yoshitsugu INOUE, Rebert STREITENBERGER, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Highly Parallel DSP Architecture for Image Recognition},
year={1995},
volume={E78-A},
number={8},
pages={963-970},
abstract={This paper presents a newly developed architecture for a highly parallel DSP suited for realtime image reaognition. The programmable DSP was designed for a variety of image recognition systems, such as computer vision systems, character recognition systems and others. The DSP consists of functional units suited for image recognition: a SIMD processing core, a hierarchical bus, an Address Generation Unit, Data Memories, a DMA controller, a Link Unit, and a Control Unit. The high performance of 3.2GOPS is realized by the eight-parallel SIMD core with a optimized pipeline structure for image recognition algorithms. The DSP supports flexible data transfers including an extraction of lacal images from raster scanned image data, a table-loop-up, a data-broadcasting, and a data-shifting among processing units in the SIMD core, for effective execution of various image processing algorithms. Hence, the DSP can process a 55 spatial filtering for 512512 images within 13.1 msec. Adopting the DSP to a Japanese character recognition system, the speed of 924 characters/sec can be achieved for feature extractions and feature vectors matchings. The DSP can be integrated in a 14.514.5 mm² single-chip, using 0.5 µm CMOS technology. In this paper, the key features of the architecture and the new techniques enabling efficient operation of the eight parallel processing units are described. Estimation of the performance of the DSP is also presented.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - A Highly Parallel DSP Architecture for Image Recognition
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 963
EP - 970
AU - Hiroyuki KAWAI
AU - Yoshitsugu INOUE
AU - Rebert STREITENBERGER
AU - Masahiko YOSHIMOTO
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E78-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 1995
AB - This paper presents a newly developed architecture for a highly parallel DSP suited for realtime image reaognition. The programmable DSP was designed for a variety of image recognition systems, such as computer vision systems, character recognition systems and others. The DSP consists of functional units suited for image recognition: a SIMD processing core, a hierarchical bus, an Address Generation Unit, Data Memories, a DMA controller, a Link Unit, and a Control Unit. The high performance of 3.2GOPS is realized by the eight-parallel SIMD core with a optimized pipeline structure for image recognition algorithms. The DSP supports flexible data transfers including an extraction of lacal images from raster scanned image data, a table-loop-up, a data-broadcasting, and a data-shifting among processing units in the SIMD core, for effective execution of various image processing algorithms. Hence, the DSP can process a 55 spatial filtering for 512512 images within 13.1 msec. Adopting the DSP to a Japanese character recognition system, the speed of 924 characters/sec can be achieved for feature extractions and feature vectors matchings. The DSP can be integrated in a 14.514.5 mm² single-chip, using 0.5 µm CMOS technology. In this paper, the key features of the architecture and the new techniques enabling efficient operation of the eight parallel processing units are described. Estimation of the performance of the DSP is also presented.
ER -