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Shigeru OHO Hisao SONOBE Jun-ichi MAKINO Hiroshi KAJIOKA Tatsuya KUMAGAI
The phase-modulated optical fiber gyroscope signal was analyzed in a time-domain. The rotation rate detected by the gyroscope optics was extracted from the gyroscope signal as time-domain characteristics at the maximum sensitivity.
Shigeru OHO Masatoshi HOSHINO Hisao SONOBE Hiroshi KAJIOKA
A down sampling technique was applied to signal processing of fiber optic gyroscopes with optical phase modulation. The technique shifts the frequency spectrum of the gyroscopic signal down to low frequencies, and lowers the speed requirements for analog-to-digital (A/D) conversion and numerical operations. A single-chip digital signal processor (DSP) with a built-in A/D converter and timers was used to demonstrate the proposed technique. The DSP internally generated a phase modulation signal and sampling trigger timing. The reference signals for digital lock-in discrimination of gyroscopic spectrum are generated by using an external binary counter, and their phases were adjusted optimally by DSP software. The DSP compensated for fluctuations in laser source intensity and phase modulation index, using the signal spectrum extracted, and linearized the gyroscopic response. The measured resolution of rotation detection was 0.9 deg/s (with a full scale of 100 deg/s) and it agreed with the resolution in A/D conversion.
Shigeru OHO Hisao SONOBE Jun-ichi MAKINO Hiroshi KAJIOKA Tatsuya KUMAGAI
A down sampling technique was applied to signal processing for optical fiber gyroscopes. It lowered the higher speed requirement for the sampling system and numerical operations. Utilizing the technique, a digital signal processing circuit extracted rotational information from the gyroscope signal.
Shigeru OHO Hisao SONOBE Jun-ichi MAKINO Hiroshi KAJIOKA Tatsuya KUMAGAI
Secondary phase modulation was proposed for lowering the signal frequency band of open-loop optical fiber gyroscopes. Extracting the lowered frequency spectra, the rotation rate was derived from the gyroscope signal and the drift in the optical parameters were compensated.
Makoto ISHIKAWA George SAIKALIS Shigeru OHO
We review practical case studies of a developing method of highly reliable real-time embedded control systems using a CPU model-based hardware/software co-simulation. We take an approach that enables us to fully simulate a virtual mechanical control system including a mechatronics plant, microcontroller hardware, and object code level software. This full virtual system approach simulates control system behavior, especially that of the microcontroller hardware and software. It enables design space exploration of microarchitecture, control design validation, robustness evaluation of the system, software optimization before components design. It also avoids potential problems. The advantage of this work is that it comprises all the components in a typical control system, enabling the designers to analyze effects from different domains, for example mechanical analysis of behavior due to differences in controller microarchitecture. To further improve system design, evaluation and analysis, we implemented an integrated behavior analyzer in the development environment. This analyzer can graphically display the processor behavior during the simulation without affecting simulation results such as task level CPU load, interrupt statistics, and the software variable transition chart. It also provides useful information on the system behavior. This virtual system analysis does not require software modification, does not change the control timing, and does not require any processing power from the target microcontroller. Therefore this method is suitable for real-time embedded control system design, in particular automotive control system design that requires a high level of reliability, robustness, quality, and safety. In this study, a Renesas SH-2A microcontroller model was developed on a CoMETTMplatform from VaST Systems Technology. An electronic throttle control (ETC) system and an engine control system were chosen to prove this concept. The electronic throttle body (ETB) model on the Saber® simulator from Synopsys® and the engine model on MATLAB®/Simulink® simulator from MathWorks can be simulated with the SH-2A model using a newly developed co-simulation interface between MATLAB®/Simulink® and CoMETTM. Though the SH-2A chip was being developed as the project was being executed, we were able to complete the OSEK OS development, control software design, and verification of the entire system using the virtual environment. After releasing a working sample chip in a later stage of the project, we found that such software could run on both actual ETC system and engine control system without critical problem. This demonstrates that our models and simulation environment are sufficiently credible and trustworthy.
Shigeru OHO Hisao SONOBE Hiroshi KAJIOKA
Time-domain characteristics of the signal of an open-loop fiber optic gyroscope were analyzed. The waveform moments of the gyroscope signal were dependent upon the rotation-induced Sagnac phase, just as the signal frequency spectra are. The peak positions of the time signal also varied with the supplied rotation, and the Sagnac phase could be read out, with optimum sensitivity, from the intervals between peaks. To demonstrate the time-domain measurement technique, the gyroscope signal was transferred to lower frequencies and the signal period was lengthened. This equivalent-time scheme lowered the operational speed requirement on the signal processing electronics and improved measurement resolution.
Go MATSUKAWA Yohei NAKATA Yasuo SUGURE Shigeru OHO Yuta KIMI Masafumi SHIMOZAWA Shuhei YOSHIDA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
This paper presents a novel architecture for a fault-tolerant and dual modular redundancy (DMR) system using a checkpoint recovery approach. The architecture features exploitation of SRAM with simultaneous copy and instantaneous compare function. It can perform low-latency data copying between dual cores. Therefore, it can carry out fast backup and rollback. Furthermore, it can reduce the power consumption during data comparison process compared to the cyclic redundancy check (CRC). Evaluation results show that, compared with the conventional checkpoint/restart DMR, the proposed architecture reduces the cycle overhead by 97.8% and achieves a 3.28% low-latency execution cycle even if a one-time fault occurs when executing the task. The proposed architecture provides high reliability for systems with a real-time requirement.