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[Author] Shuhei YOSHIDA(4hit)

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  • Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path

    Go MATSUKAWA  Yuta KIMI  Shuhei YOSHIDA  Shintaro IZUMI  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E99-A No:6
      Page(s):
    1198-1205

    As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.5%, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.7% on average.

  • Multi-Dimensional Shift Multiplexing Technique with Spherical Reference Waves

    Shuhei YOSHIDA  Takaaki MATSUBARA  Hiroyuki KURATA  Shuma HORIUCHI  Manabu YAMAMOTO  

     
    PAPER

      Vol:
    E96-C No:12
      Page(s):
    1520-1524

    Holographic data storage (HDS) is a next-generation optical storage that uses the principles of holography. The multiplex holographic recording method is an important factor that affects the recording capacity of this storage. Various multiplex recording methods have been proposed so far. In this study, we focus on shift multiplexing with spherical waves and propose a method of shift multiplex recording that combines the in-plane direction and thickness direction of the recording medium. In conventional shift multiplexing with spherical waves, shift multiplexing is usually carried out with respect to the direction parallel to the plane of the recording medium. By focusing on the fact that shift selectivity is also in the thickness direction, we examined the possibility of a multiplex recording method that combines multiple shift directions. Simulation and experimental verification shows that the proposed method is effective in principle.

  • Computer Simulation Analysis of Speckle-Shift Multiplexed Recording in Holographic Memory

    Takumi SANO  Fuminori NAITO  Shuhei YOSHIDA  Manabu YAMAMOTO  

     
    PAPER

      Vol:
    E90-C No:8
      Page(s):
    1606-1611

    In this paper, we presented a computer simulation analysis of high-density hologram recording, which is a promising mass optical memory technique. A simulation method for off-axis speckle-shift multiplexed recording by three-dimensional computer simulation analysis was presented, as well the signal evaluation of recording and reproduction. By this simulation method, the characteristic features of recording and reproduction are studied from the viewpoints of signal-to-noise-ratio and the reproduced image's quality, and a high-density speckle-shift multiplexed recording condition is proposed.

  • A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

    Go MATSUKAWA  Yohei NAKATA  Yasuo SUGURE  Shigeru OHO  Yuta KIMI  Masafumi SHIMOZAWA  Shuhei YOSHIDA  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO  

     
    PAPER

      Vol:
    E98-C No:4
      Page(s):
    333-339

    This paper presents a novel architecture for a fault-tolerant and dual modular redundancy (DMR) system using a checkpoint recovery approach. The architecture features exploitation of SRAM with simultaneous copy and instantaneous compare function. It can perform low-latency data copying between dual cores. Therefore, it can carry out fast backup and rollback. Furthermore, it can reduce the power consumption during data comparison process compared to the cyclic redundancy check (CRC). Evaluation results show that, compared with the conventional checkpoint/restart DMR, the proposed architecture reduces the cycle overhead by 97.8% and achieves a 3.28% low-latency execution cycle even if a one-time fault occurs when executing the task. The proposed architecture provides high reliability for systems with a real-time requirement.