IEICE TRANSACTIONS on Fundamentals
Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path
Summary :
As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.5%, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.7% on average.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.6 pp.1198-1205
- Publication Date
- 2016/06/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E99.A.1198
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Go MATSUKAWA
Kobe University
Yuta KIMI
Kobe University
Shuhei YOSHIDA
Kobe University
Shintaro IZUMI
Kobe University
Hiroshi KAWAGUCHI
Kobe University
Masahiko YOSHIMOTO
Kobe University
Keyword
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Go MATSUKAWA, Yuta KIMI, Shuhei YOSHIDA, Shintaro IZUMI, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, "Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path" in IEICE TRANSACTIONS on Fundamentals,
vol. E99-A, no. 6, pp. 1198-1205, June 2016, doi: 10.1587/transfun.E99.A.1198.
Abstract: As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.5%, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.7% on average.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.1198/_p
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@ARTICLE{e99-a_6_1198,
author={Go MATSUKAWA, Yuta KIMI, Shuhei YOSHIDA, Shintaro IZUMI, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path},
year={2016},
volume={E99-A},
number={6},
pages={1198-1205},
abstract={As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.5%, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.7% on average.},
keywords={},
doi={10.1587/transfun.E99.A.1198},
ISSN={1745-1337},
month={June},}
Copy
TY - JOUR
TI - Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1198
EP - 1205
AU - Go MATSUKAWA
AU - Yuta KIMI
AU - Shuhei YOSHIDA
AU - Shintaro IZUMI
AU - Hiroshi KAWAGUCHI
AU - Masahiko YOSHIMOTO
PY - 2016
DO - 10.1587/transfun.E99.A.1198
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2016
AB - As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.5%, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.7% on average.
ER -
English
