The objective, when mapping a wafer, is to capture the the full variation across the wafer while minimising the number of measurements. This is a very similar objective to that of experimental design and this paper applies classical Design Of Experiment (DOE) techniques to the selection of measurement points for wafer mapping. The resulting measurements are then fitted using Response Surface Methodology (RSM) from which contour plots or wafer maps can be generated. The accuracy of the fit can be ascertained by inspection of the adjusted R2 value and it is demonstrated that in many cases transformations can be used to improve the accuracy of the resulting wafer maps.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Anthony J. WALTON, Martin FALLON, David WILSON, "The Application of DOE and RSM Techniques for Wafer Mapping in IC Technology" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 2, pp. 219-225, February 1996, doi: .
Abstract: The objective, when mapping a wafer, is to capture the the full variation across the wafer while minimising the number of measurements. This is a very similar objective to that of experimental design and this paper applies classical Design Of Experiment (DOE) techniques to the selection of measurement points for wafer mapping. The resulting measurements are then fitted using Response Surface Methodology (RSM) from which contour plots or wafer maps can be generated. The accuracy of the fit can be ascertained by inspection of the adjusted R2 value and it is demonstrated that in many cases transformations can be used to improve the accuracy of the resulting wafer maps.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_2_219/_p
Copy
@ARTICLE{e79-c_2_219,
author={Anthony J. WALTON, Martin FALLON, David WILSON, },
journal={IEICE TRANSACTIONS on Electronics},
title={The Application of DOE and RSM Techniques for Wafer Mapping in IC Technology},
year={1996},
volume={E79-C},
number={2},
pages={219-225},
abstract={The objective, when mapping a wafer, is to capture the the full variation across the wafer while minimising the number of measurements. This is a very similar objective to that of experimental design and this paper applies classical Design Of Experiment (DOE) techniques to the selection of measurement points for wafer mapping. The resulting measurements are then fitted using Response Surface Methodology (RSM) from which contour plots or wafer maps can be generated. The accuracy of the fit can be ascertained by inspection of the adjusted R2 value and it is demonstrated that in many cases transformations can be used to improve the accuracy of the resulting wafer maps.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - The Application of DOE and RSM Techniques for Wafer Mapping in IC Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 219
EP - 225
AU - Anthony J. WALTON
AU - Martin FALLON
AU - David WILSON
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 1996
AB - The objective, when mapping a wafer, is to capture the the full variation across the wafer while minimising the number of measurements. This is a very similar objective to that of experimental design and this paper applies classical Design Of Experiment (DOE) techniques to the selection of measurement points for wafer mapping. The resulting measurements are then fitted using Response Surface Methodology (RSM) from which contour plots or wafer maps can be generated. The accuracy of the fit can be ascertained by inspection of the adjusted R2 value and it is demonstrated that in many cases transformations can be used to improve the accuracy of the resulting wafer maps.
ER -