A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers
Summary :
In this paper, a high-speed PLA based on dynamic array logic circuits with latch sense amplifiers is presented. The present circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By using a charge sharing scheme and latch sense amplifiers, voltage swings of the bit-lines are reduced compared to the conventional circuits, thus a high-speed and low-power operation is achieved. The present array logic configuration can realize any logic function expressed in the sum-of-products form by using PLA structure. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-µm double-poly triple-metal CMOS process. Results of HSPICE simulation show a better performance compared to the conventional circuits. Functional testing using electron beam probing shows that the present circuit operates correctly.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E84-C No.9 pp.1240-1246
- Publication Date
- 2001/09/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
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Hiroaki YAMAOKA, Makoto IKEDA, Kunihiro ASADA, "A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 9, pp. 1240-1246, September 2001, doi: .
Abstract: In this paper, a high-speed PLA based on dynamic array logic circuits with latch sense amplifiers is presented. The present circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By using a charge sharing scheme and latch sense amplifiers, voltage swings of the bit-lines are reduced compared to the conventional circuits, thus a high-speed and low-power operation is achieved. The present array logic configuration can realize any logic function expressed in the sum-of-products form by using PLA structure. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-µm double-poly triple-metal CMOS process. Results of HSPICE simulation show a better performance compared to the conventional circuits. Functional testing using electron beam probing shows that the present circuit operates correctly.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_9_1240/_p
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@ARTICLE{e84-c_9_1240,
author={Hiroaki YAMAOKA, Makoto IKEDA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers},
year={2001},
volume={E84-C},
number={9},
pages={1240-1246},
abstract={In this paper, a high-speed PLA based on dynamic array logic circuits with latch sense amplifiers is presented. The present circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By using a charge sharing scheme and latch sense amplifiers, voltage swings of the bit-lines are reduced compared to the conventional circuits, thus a high-speed and low-power operation is achieved. The present array logic configuration can realize any logic function expressed in the sum-of-products form by using PLA structure. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-µm double-poly triple-metal CMOS process. Results of HSPICE simulation show a better performance compared to the conventional circuits. Functional testing using electron beam probing shows that the present circuit operates correctly.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers
T2 - IEICE TRANSACTIONS on Electronics
SP - 1240
EP - 1246
AU - Hiroaki YAMAOKA
AU - Makoto IKEDA
AU - Kunihiro ASADA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2001
AB - In this paper, a high-speed PLA based on dynamic array logic circuits with latch sense amplifiers is presented. The present circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By using a charge sharing scheme and latch sense amplifiers, voltage swings of the bit-lines are reduced compared to the conventional circuits, thus a high-speed and low-power operation is achieved. The present array logic configuration can realize any logic function expressed in the sum-of-products form by using PLA structure. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-µm double-poly triple-metal CMOS process. Results of HSPICE simulation show a better performance compared to the conventional circuits. Functional testing using electron beam probing shows that the present circuit operates correctly.
ER -
English
