A Cost-Effective Handshake Protocol and Its Implementation for Bundled-Data Asynchronous Circuits
Summary :
We propose and implement a four-phase handshake protocol for bundled-data asynchronous circuits with consideration given to power consumption and area. A key aspect is that our protocol uses three phases for generating the matched delay to signal the completion of the data-path stage operation whereas conventional methods use only one phase. A comparison with other protocols at 0.18 µm process showed that our protocol realized lower power consumption than any other protocol at cycle times of 1.2 ns or more. The area of the delay generator required for a given data-path delay was less than half that of other protocols. The overhead of the timing generator was the same as or less than that of other protocols.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.1 pp.280-287
- Publication Date
- 2006/01/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.1.280
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Masakazu SHIMIZU, Koki ABE, "A Cost-Effective Handshake Protocol and Its Implementation for Bundled-Data Asynchronous Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 1, pp. 280-287, January 2006, doi: 10.1093/ietfec/e89-a.1.280.
Abstract: We propose and implement a four-phase handshake protocol for bundled-data asynchronous circuits with consideration given to power consumption and area. A key aspect is that our protocol uses three phases for generating the matched delay to signal the completion of the data-path stage operation whereas conventional methods use only one phase. A comparison with other protocols at 0.18 µm process showed that our protocol realized lower power consumption than any other protocol at cycle times of 1.2 ns or more. The area of the delay generator required for a given data-path delay was less than half that of other protocols. The overhead of the timing generator was the same as or less than that of other protocols.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.1.280/_p
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@ARTICLE{e89-a_1_280,
author={Masakazu SHIMIZU, Koki ABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Cost-Effective Handshake Protocol and Its Implementation for Bundled-Data Asynchronous Circuits},
year={2006},
volume={E89-A},
number={1},
pages={280-287},
abstract={We propose and implement a four-phase handshake protocol for bundled-data asynchronous circuits with consideration given to power consumption and area. A key aspect is that our protocol uses three phases for generating the matched delay to signal the completion of the data-path stage operation whereas conventional methods use only one phase. A comparison with other protocols at 0.18 µm process showed that our protocol realized lower power consumption than any other protocol at cycle times of 1.2 ns or more. The area of the delay generator required for a given data-path delay was less than half that of other protocols. The overhead of the timing generator was the same as or less than that of other protocols.},
keywords={},
doi={10.1093/ietfec/e89-a.1.280},
ISSN={1745-1337},
month={January},}
Copy
TY - JOUR
TI - A Cost-Effective Handshake Protocol and Its Implementation for Bundled-Data Asynchronous Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 280
EP - 287
AU - Masakazu SHIMIZU
AU - Koki ABE
PY - 2006
DO - 10.1093/ietfec/e89-a.1.280
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2006
AB - We propose and implement a four-phase handshake protocol for bundled-data asynchronous circuits with consideration given to power consumption and area. A key aspect is that our protocol uses three phases for generating the matched delay to signal the completion of the data-path stage operation whereas conventional methods use only one phase. A comparison with other protocols at 0.18 µm process showed that our protocol realized lower power consumption than any other protocol at cycle times of 1.2 ns or more. The area of the delay generator required for a given data-path delay was less than half that of other protocols. The overhead of the timing generator was the same as or less than that of other protocols.
ER -
English
