Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit

Masayuki UNO; Shoji KAWAHITO

doi:10.1093/ietele/e89-c.6.702

Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit

Masayuki UNO, Shoji KAWAHITO

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This paper describes the design of a small-offset 12-bit CMOS charge-redistribution DAC using a weighted-mean flip-around sample-and-hold circuit (S/H). Flip-around S/H topology can realize small-offset characteristics, and it is effective to reduce power dissipation and chip area because independent feedback capacitors are not necessary. In this DAC the small-offset characteristic remains not only in amplification phase but also in sampling phase with the circuit technique. The design of 1.8 V, 50 MS/s fully differential DAC with output swing of 2 Vp-p has very small offset of 100 µV for the reset switch mismatch of 2%. A technique to improve dynamic performance measured by SFDR using damping resistors and switches at the output stage is also presented. The designed 12-bit DAC with 0.25 µm CMOS technology has low-power dissipation of 35 mW at 50 MS/s.

Publication: IEICE TRANSACTIONS on Electronics Vol.E89-C No.6 pp.702-709

Publication Date: 2006/06/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e89-c.6.702

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies)

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Masayuki UNO, Shoji KAWAHITO, "Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit" in IEICE TRANSACTIONS on Electronics, vol. E89-C, no. 6, pp. 702-709, June 2006, doi: 10.1093/ietele/e89-c.6.702.
Abstract: This paper describes the design of a small-offset 12-bit CMOS charge-redistribution DAC using a weighted-mean flip-around sample-and-hold circuit (S/H). Flip-around S/H topology can realize small-offset characteristics, and it is effective to reduce power dissipation and chip area because independent feedback capacitors are not necessary. In this DAC the small-offset characteristic remains not only in amplification phase but also in sampling phase with the circuit technique. The design of 1.8 V, 50 MS/s fully differential DAC with output swing of 2 Vp-p has very small offset of 100 µV for the reset switch mismatch of 2%. A technique to improve dynamic performance measured by SFDR using damping resistors and switches at the output stage is also presented. The designed 12-bit DAC with 0.25 µm CMOS technology has low-power dissipation of 35 mW at 50 MS/s.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.6.702/_p

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@ARTICLE{e89-c_6_702,
author={Masayuki UNO, Shoji KAWAHITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit},
year={2006},
volume={E89-C},
number={6},
pages={702-709},
abstract={This paper describes the design of a small-offset 12-bit CMOS charge-redistribution DAC using a weighted-mean flip-around sample-and-hold circuit (S/H). Flip-around S/H topology can realize small-offset characteristics, and it is effective to reduce power dissipation and chip area because independent feedback capacitors are not necessary. In this DAC the small-offset characteristic remains not only in amplification phase but also in sampling phase with the circuit technique. The design of 1.8 V, 50 MS/s fully differential DAC with output swing of 2 Vp-p has very small offset of 100 µV for the reset switch mismatch of 2%. A technique to improve dynamic performance measured by SFDR using damping resistors and switches at the output stage is also presented. The designed 12-bit DAC with 0.25 µm CMOS technology has low-power dissipation of 35 mW at 50 MS/s.},
keywords={},
doi={10.1093/ietele/e89-c.6.702},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 702
EP - 709
AU - Masayuki UNO
AU - Shoji KAWAHITO
PY - 2006
DO - 10.1093/ietele/e89-c.6.702
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2006
AB - This paper describes the design of a small-offset 12-bit CMOS charge-redistribution DAC using a weighted-mean flip-around sample-and-hold circuit (S/H). Flip-around S/H topology can realize small-offset characteristics, and it is effective to reduce power dissipation and chip area because independent feedback capacitors are not necessary. In this DAC the small-offset characteristic remains not only in amplification phase but also in sampling phase with the circuit technique. The design of 1.8 V, 50 MS/s fully differential DAC with output swing of 2 Vp-p has very small offset of 100 µV for the reset switch mismatch of 2%. A technique to improve dynamic performance measured by SFDR using damping resistors and switches at the output stage is also presented. The designed 12-bit DAC with 0.25 µm CMOS technology has low-power dissipation of 35 mW at 50 MS/s.
ER -