We found a new class of stochastic resonance (SR) in a simple neural network that consists of i) photoreceptors generating nonuniform outputs for common inputs with random offsets, ii) an ensemble of noisy McCulloch-Pitts (MP) neurons each of which has random threshold values in the temporal domain, iii) local coupling connections between the photoreceptors and the MP neurons with variable receptive fields (RFs), iv) output cells, and v) local coupling connections between the MP neurons and the output cells. We calculated correlation values between the inputs and the outputs as a function of the RF size and intensities of the random components in photoreceptors and the MP neurons. We show the existence of "optimal noise intensities" of the MP neurons under the nonidentical photoreceptors and "nonzero optimal RF sizes," which indicated that optimal correlation values of this SR model were determined by two critical parameters; noise intensities (well-known) and RF sizes as a new parameter.

We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulse-density modulation (PDM) with noisy neural elements, with the aim of developing a possible ultralow-power one-bit analog-to-digital converter. The static and dynamic noises given to the proposed circuits were obtained from device mismatches of current sources (transistors) and externally applied random spike currents, respectively. Through circuit simulations we confirmed that the circuit exhibited noise-shaping properties, and signal-to-noise ratio (SNR) of the network was improved by 7.9 dB compared with that of the uncoupled network as a result of noise shaping.

We present on-chip oscillator arrays synchronized by random noises, aiming at skew-free clock distribution on synchronous digital systems. Nakao et al. recently reported that independent neural oscillators can be synchronized by applying temporal random impulses to the oscillators [1],[2]. We regard neural oscillators as independent clock sources on LSIs; i.e., clock sources are distributed on LSIs, and they are forced to synchronize through the use of random noises. We designed neuron-based clock generators operating at sub-RF region (< 1 GHz) by modifying the original neuron model to a new model that is suitable for CMOS implementation with 0.25-µm CMOS parameters. Through circuit simulations, we demonstrate that i) the clock generators are certainly synchronized by pseudo-random noises and ii) clock generators exhibited phase-locked oscillations even if they had small device mismatches.